3D Memory Select Gate Stacking for Reduced Planar Area
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently selecting and controlling multiple string units within a three-dimensional memory cell array, leading to increased complexity and reduced access times due to the wide widths of separation portions and high resistance in select gate layers.
Innovation Solution
The semiconductor memory device employs a configuration with stacked layers of select gates and word lines, where select gates are divided by narrower separation portions, allowing for independent control of each string unit and reducing the number of separation portions, thereby improving access times and reducing the planar size of the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wider separation portions are used to divide select gates, then easier manufacturing and control are achieved, but the planar size of the memory cell array increases and access times are reduced
Solution Approach 1:
The patent transitions from planar separation to vertical stacking by configuring select gates in multiple layers (first select gate layer and second select gate layer). This dimensional change allows separation portions to be narrower while still achieving effective gate control through the stacked arrangement, thereby reducing the planar area without compromising manufacturability.
Solution Approach 2:
The select gate function is segmented across multiple layers with different select gates (first select gates and second select gates) positioned at different heights. This segmentation allows independent control of different string units through selective activation of gates in different layers, maintaining ease of control while using narrower separation portions.
2Reliability
If more separation portions are added to control multiple string units, then better selectivity is achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of adding more separation portions in the planar direction, the patent utilizes the vertical dimension by stacking select gates in multiple layers. This allows the same number of select gates to control more string units by selecting different combinations of gates across layers, achieving better selectivity without increasing device complexity.
Solution Approach 2:
Each select gate layer serves multiple functions by controlling different string units when combined with other layers. The first select gates and second select gates work together in a multi-functional arrangement where fewer separation portions are needed because each gate participates in controlling multiple string units through different combinations.
3Loss of time
If select gates are controlled independently with more separation portions, then better access time is achieved, but the resistance in select gate layers increases
Solution Approach 1:
The stacked configuration of select gates in vertical layers provides multiple parallel conduction paths for select gate signals. This dimensional arrangement reduces the effective resistance by distributing the current across multiple gates in series, allowing faster access times without excessive resistance increase compared to a single-planar arrangement.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n−1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n−1) layers of select gate layers include first to (2×(n−1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n−1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k−2)th select gates. The nth string unit is selected by the nth to (2×(n−1))th select gates.