3D Memory Select-Gate Structure for Precise Via Coupling
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming vertically-stacked memory cells with precise control over the distance between select-gate channel material and conductive vias, leading to suboptimal electrical coupling and potential shorting issues.
Innovation Solution
A method involving simultaneous deposition of storage material, insulative charge-passage material, and channel material in both upper and lower channel openings, followed by selective etching to form select gates, ensuring precise control and direct electrical coupling of channel material with conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory formation methods are used, then manufacturing process is simpler, but electrical coupling between channel material and vias is suboptimal
Solution Approach 1:
The patent applies preliminary action by forming the channel material in the lower channel opening before forming the select gate structure above it. This sequential approach ensures that the channel material is already in place and properly positioned before subsequent layers are added, enabling precise control over the distance between the channel material and the conductive via, thereby optimizing electrical coupling without requiring complex post-processing adjustments
2Reliability
If precise control over distance between channel material and vias is implemented, then electrical coupling is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the select gate structure: it serves as both the gate electrode and the conductive via connection element. By combining these functions into a single integrated structure formed through sequential deposition and patterning steps, the patent achieves precise distance control and enhanced electrical coupling without requiring separate complex processes for gate formation and via formation
3Ease of manufacture
If distance between channel material and vias is not precisely controlled, then manufacturing is easier, but shorting risks increase
Solution Approach 1:
The patent applies local quality by creating distinct regions with different material properties and geometries: the channel material in the lower opening, the insulative charge-passage material, and the select gate structure above. This localized differentiation of materials and structures ensures proper spacing and electrical isolation in critical areas while maintaining manufacturing feasibility through standard deposition and etching processes
Data Source
AI summary
A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.