Non-Volatile Memory Cell Select Gates for Low-Voltage Fast Operation
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Solution Overview
Problem
Conventional memory cells require high bit voltages to prevent charge injection into the charge storage layer, leading to increased thickness of select gate insulating films and peripheral circuit area, which hinders high-speed operation.
Innovation Solution
Reducing the voltages applied to the bit line and source line allows the select gate structures to block electrical connections, thereby reducing the thickness of select gate insulating films and achieving high-speed operation without the need for thick gate insulating films in peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high bit voltage is applied to prevent charge injection into the charge storage layer, then charge injection is prevented, but the thickness of the select gate insulating film must be increased
Solution Approach 1:
The patent changes the voltage parameter from high bit voltage to low bit voltage combined with controlled channel layer potential. Instead of applying high voltage to the bit line, the invention controls the channel layer potential to be close to the bit line potential, achieving charge injection prevention through parameter optimization rather than high voltage stress.
Solution Approach 2:
The channel layer acts as an intermediary between the bit line and the memory gate structure. By controlling the channel layer potential, the invention mediates the voltage relationship, allowing low bit voltage to suffice while preventing charge injection through potential control of the intermediate channel layer.
2Reliability
If a high bit voltage is applied to prevent charge injection, then charge injection is prevented, but the area of peripheral circuits must be increased
Solution Approach 1:
The invention changes the voltage parameter from high to low, which directly reduces the area requirements for peripheral circuits. Gate insulating films in peripheral circuits can be thinner when low voltages are used, reducing the overall circuit area while maintaining charge injection prevention through channel layer potential control.
3Reliability
If a high bit voltage is applied to prevent charge injection, then charge injection is prevented, but operation speed is reduced
Solution Approach 1:
By changing from high voltage operation to low voltage operation with controlled potential differences, the invention improves operation speed. Thinner gate insulating films enabled by low voltage operation reduce capacitance and improve switching speed, while charge injection prevention is achieved through potential control rather than voltage magnitude.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster operation and reduces the area of peripheral circuits by minimizing the thickness of select gate insulating films, while preventing charge injection into unintended memory cells.
Implementation Method 1
Charge is injected into the charge storage layer by a quantum tunneling effect caused by a voltage difference between the bit voltage and the memory gate voltage.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A voltage applied to a bit line (BL1) or a voltage applied to a source line (SL) is reduced to a value that allows a first select gate structure (5) or a second select gate structure (6) to block electrical connection between the bit line (BL1) and a channel layer (CH) or between the source line (SL) and the channel layer (CH), irrespective of a charge storage gate voltage needed to inject charge into a charge storage layer (EC) by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a first select gate insulating film (30) of the first select gate structure (5) and thickness of a second select gate insulating film (33) of the second select gate structure (6) are reduced. High-speed operation is achieved correspondingly. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a gate insulating film of a field effect transistor in a peripheral circuit that controls a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.