Memory Device Select Line Floating Timing for Erase Speed Compensation
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Solution Overview
Problem
Memory devices face challenges in compensating for erase speed differences among memory cell strings, leading to inefficiencies in data erasure operations.
Innovation Solution
The implementation of a memory device with control logic that manages the floating of select lines connected to select transistors based on erase speed information, ensuring that strings with slower erase speeds are compensated by adjusting the timing of when select lines are floated during the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operation is performed on multiple memory cell strings simultaneously, then productivity is improved, but erase speed difference among strings causes reliability degradation
Solution Approach 1:
The patent segments the erase operation into multiple phases with different voltage application strategies. Different memory cell strings are divided into groups (first group, second group, etc.) that receive erase voltages at different timings. This segmentation allows simultaneous erosion of multiple strings while accounting for individual string characteristics, resolving the contradiction between high-speed parallel erasure and complete erase reliability.
Solution Approach 2:
The patent changes voltage parameters dynamically during the erase operation. Erase voltages are applied at different timings to different string groups, and voltages are adjusted based on string erase speeds. This parameter variation enables fast strings to be erased completely while slower strings receive extended or intensified erase voltage, ensuring all strings achieve complete erasure without sacrificing overall productivity.
2Productivity
If erase voltage is applied to all strings simultaneously, then productivity is improved, but strings with slower erase speeds remain incompletely erased causing reliability issues
Solution Approach 1:
The patent applies local quality by treating different memory cell strings with different erase voltage timings based on their individual characteristics. Fast-erasing strings receive standard erase voltage timing, while slow-erasing strings are identified and given extended or delayed erase voltage application. This localized differentiation ensures each string receives appropriate erase treatment, achieving uniform erase completeness across all strings while maintaining high overall erase efficiency.
Solution Approach 2:
The patent incorporates feedback mechanisms to monitor erase progress and adjust voltage application accordingly. Erase status is detected during the operation, and this information feeds back to control the timing and duration of erase voltages applied to different string groups. This feedback loop enables dynamic adjustment to compensate for erase speed variations, ensuring complete erasure of all strings while optimizing the overall erase process speed.
3Speed
If select lines are floated immediately after erase voltage application, then operation speed is improved, but strings with slower erase speeds do not complete erasure causing reliability degradation
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the erase speeds of different memory cell strings before the actual erase operation. Based on this preliminary information, the control logic pre-plans the timing of select line floating for different string groups. Strings identified as slower erasers are assigned delayed select line floating timing, ensuring they receive sufficient erase voltage duration. This preliminary preparation enables the system to maintain fast overall erase speed while guaranteeing complete erasure of all strings.
Solution Approach 2:
The patent introduces dynamics by making the select line floating timing variable rather than fixed. The timing of select line floating is dynamically adjusted based on the erase speed characteristics of different string groups. Fast strings have their select lines floated earlier, while slow strings have their select lines floated later. This dynamic adaptation allows the system to optimize erase speed for each individual string, resolving the contradiction between overall operation speed and individual string erase completion.
Data Source
AI summary
A memory device includes: a first string including a plurality of first memory cells, and a first select transistor connected between a first conductive line and the plurality of first memory cells; a second string including a plurality of second memory cells, and a second select transistor connected between the first conductive line and the plurality of second memory cells; a peripheral circuit configured to perform an erase operation of the first and second strings; and control logic. The control logic is configured to control the peripheral circuit to, during the erase operation, apply a first erase voltage to the first conductive line, float a first select line connected to the first select transistor after the first erase voltage is applied, and float a second select line connected to the second select transistor after the first select line is floated.