3D Memory Select-Line Layout for Lower Cell Interference
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Solution Overview
Problem
Three-dimensional memory devices face challenges in increasing integration density while minimizing interference between memory cells, which can occur due to reduced distances between stacked memory cells.
Innovation Solution
The memory device incorporates a first and second memory block structure with shared source select lines and a connection region, utilizing source select lines that are selectively turned on or off to reduce interference by minimizing current flow in unselected strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells stacked on top of each other is increased to improve integration density, then the integration density is improved, but the distance between memory cells is reduced causing increased interference between memory cells
Solution Approach 1:
The memory block is divided into multiple string groups (first string group, second string group, third string group, fourth string group) with different select line configurations. Each group can be independently controlled, allowing selective activation of specific memory regions while keeping others in high-impedance state, thereby reducing interference between adjacent memory cells.
Solution Approach 2:
The select lines (first source select line, second source select line, third source select line) are dynamically controlled to be selectively turned on or off. During operation, only the select lines corresponding to the actively accessed memory strings are enabled, while others are disabled. This dynamic control minimizes current flow in unselected strings and reduces interference between memory cells.
2Area of stationary object
If the distance between memory cells is reduced to increase integration density, then the device size is reduced, but interference between memory cells is increased
Solution Approach 1:
The memory structure is segmented into distinct string groups with dedicated select line control. This segmentation allows close physical spacing of memory cells while maintaining electrical isolation through selective gating, enabling high integration density without proportionally increasing interference.
Solution Approach 2:
The electrical state of select lines is changed dynamically between active and high-impedance states. By changing the electrical parameters (voltage levels, impedance states) of the select lines, the patent controls current flow paths to minimize interference even when memory cells are closely spaced.
3Device complexity
If source select lines are commonly coupled to multiple memory blocks to reduce device complexity, then the number of select lines is reduced, but current flow in unselected strings cannot be minimized
Solution Approach 1:
Different portions of the memory block (different string groups) are assigned different select line control configurations. The first and third string groups share the first source select line, while the second and fourth string groups have dedicated second and third source select lines respectively. This local differentiation allows selective control of current flow in different regions, minimizing energy loss in unselected strings while maintaining reasonable device complexity.
Data Source
AI summary
The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.