Memory Select Register for Operand Mapping in Subroutines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processors face challenges in supporting generic subroutines that can access operands from any of multiple local memories without incurring expensive data movement or requiring multiple subroutine copies, due to the complexity of managing multiple local memories in application-specific processors.
Innovation Solution
The processor employs a memory select register that maps virtual memory select values to physical memory select values, allowing subroutines to operate on operands in any of the data memories by updating the memory select register during subroutine calls and returns, and using a memory control field to bypass or use the memory select mapping as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple local memories are used to store input data, then data storage capacity and flexibility are improved, but the complexity of managing operand mapping in subroutines increases
Solution Approach 1:
The patent introduces a memory select register as an intermediary component that maps virtual memory select values to physical memory select values. This register acts as a mediator between the instruction stream and the multiple local memories, allowing subroutines to access operands from any local memory without complex mapping logic in the subroutine code itself. The memory select register translates generic memory access requests into specific physical memory selections, thereby reducing operand mapping complexity while maintaining support for multiple local memories.
2Adaptability or versatility
If data is stored in different local memories for different calling programs, then data organization flexibility is improved, but data movement cost increases
Solution Approach 1:
The patent creates a universal subroutine interface that can operate on data from any local memory without requiring data movement. The memory select register enables a single subroutine to be called with arguments in different local memories by dynamically updating the register mapping before subroutine execution. This eliminates the need for multiple subroutine copies or data movement between memories, as the same subroutine can adapt to different data locations through the memory select register configuration.
3Adaptability or versatility
If multiple copies of subroutines are created for different memory configurations, then subroutine functionality is improved, but code size and maintenance complexity increase
Solution Approach 1:
The patent implements dynamic memory selection through the memory select register, which can be updated at runtime based on the calling context. Instead of having static, hard-coded memory mappings in multiple subroutine copies, the system uses a single subroutine that dynamically adapts to different memory configurations through register updates. This dynamic approach allows one subroutine to serve multiple memory configurations, reducing code size and simplifying maintenance while maintaining full compatibility across different memory arrangements.
Data Source
AI summary
A processor may include a plurality of data memories storing operands that may be operated upon by the processor. Load/store operations may specify a memory location in one of the data memories to be accessed using a memory select value that selects the data memory and an address within the selected data memory. The memory select values may be mapped from virtual memory select values associated with the load/store operations to physical memory select values that may be used to access the data memory.