Semiconductor Memory Select Transistor Erase Count Management
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Solution Overview
Problem
Semiconductor memory devices experience reliability deterioration due to repeated erase operations, as the erase operation voltage applied to select transistors leads to gate-induced drain leakage (GIDL) current, causing transistor degradation.
Innovation Solution
A controller is used to monitor and manage the erase count value for each memory block, selectively applying the erase operation voltage to specific select transistors based on the erase count, dispersing the deterioration across multiple transistors to prevent reliability degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operation voltage is applied to select transistors during erase operations, then erase operation can be performed, but gate-induced drain leakage current causes transistor degradation and reliability deterioration
Solution Approach 1:
The select transistors are divided into multiple groups (first select transistor group and second select transistor group). During erase operations, voltage is applied to only one group at a time based on the erase count, segmenting the stress exposure and preventing all transistors from degrading simultaneously. This segmentation allows the memory device to perform erase operations while distributing the degradation across different transistor groups at different times.
2Productivity
If erase operations are repeated, then data storage capacity is maintained through reformatting, but transistor leakage current characteristics deteriorate
Solution Approach 1:
The controller periodically switches between different select transistor groups for voltage application during erase operations, based on an erase count that tracks the number of erase operations performed. This periodic switching ensures that no single group of transistors is continuously subjected to stress, allowing periodic recovery and maintaining overall device reliability while enabling repeated data storage operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents reliability deterioration of semiconductor memory devices by selectively using select transistors during erase operations, reducing the impact of repeated program-erase cycles on transistor leakage current characteristics.
Implementation Method 1
the erase operation voltage applied to select transistors leads to gate-induced drain leakage (GIDL) current, causing transistor degradation
Data Source
AI summary
There may be provided a controller including an erase count monitor and a command generator. The erase count monitor may store and update an erase count value for the memory block. The erase count value may indicate a number of times an erase operation is performed for the memory block. The command generator may be configured to generate, based on the erase count value, a set command for setting a first select transistor among the select transistors to which an erase operation voltage is to be applied during the erase operation of the memory block, and a second select transistor among the select transistors to be floated when the erase operation voltage is to be applied to the first select transistor.