Memory Device Select Voltage Overshoot Management

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Solution Overview

Problem

Current memory devices face challenges in managing overshoot and rising time during select voltage application, which can lead to inefficiencies in data storage and retrieval operations.

Innovation Solution

The method involves applying a select voltage to a select line in a memory device, with voltage levels and timing determined based on the number of unselected cell strings and the distance between the select line and the selected word line, using a program operation controller to manage the select voltage and minimize overshoot and rising time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a select voltage is applied to the select line during program operation, then the program operation can be performed, but overshoot occurs on the select line causing inefficiencies

Engineering Contradiction:
Improveprogram operation reliabilityVSAvoidovershoot magnitude
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies a preliminary select voltage to the select line before applying the program voltage to the word line. This preliminary voltage application prepares the select transistor channel in advance, ensuring it is fully conductive when the program operation begins, thereby preventing overshoot caused by delayed channel formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts the select voltage timing based on the specific program operation requirements. The select voltage is applied at an optimized time relative to the program voltage, and its duration is dynamically controlled to maintain the select transistor in a conductive state throughout the program operation without causing overshoot.

Inventive Principle:
Principle #15Dynamics

2Reliability

If a select voltage is applied to the select line during program operation, then the program operation can be performed, but the rising time of the select voltage increases operation time

Engineering Contradiction:
Improveprogram operation reliabilityVSAvoidrising time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The select voltage is applied in advance before the program voltage, allowing the select transistor channel to form and stabilize prior to the actual program operation. This preliminary action reduces the effective rising time during the critical program operation phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent optimizes the select voltage parameters including its amplitude, duration, and timing relative to the program voltage. By carefully controlling these parameters, the rising time is minimized while ensuring the select transistor is fully conductive during the program operation.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the select voltage level is increased to improve program operation, then program efficiency improves, but overshoot magnitude increases

Engineering Contradiction:
Improveprogram operation efficiencyVSAvoidovershoot magnitude
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

By applying the select voltage in advance at an appropriate level, the select transistor channel is gradually formed and stabilized. This prevents the need for sudden high-voltage application that would cause overshoot, while still achieving full program operation efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The select voltage is dynamically timed and controlled throughout the program operation. The voltage is maintained at an optimal level during the critical program phase to ensure efficiency, while the timing and duration are controlled to prevent overshoot conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11404100B2Memory device and method of operating the same
Publication Date: 2022.08.02 SK HYNIX INC
  • US11404100B2 patent drawing
  • US11404100B2 patent drawing
  • US11404100B2 patent drawing

AI summary

Provided herein may be a memory device having improved overshoot management performance, and a method of operating the memory device. The method may include: applying a select voltage to a select line coupled in common to respective select transistors in a plurality of cell strings; and applying a program voltage to a selected word line coupled in common to selected memory cells among a plurality of memory cells in the plurality of cell strings. The applying of the select voltage may include applying a first select voltage to the select line during a first time period. The applying of the program voltage may include applying, to the select line, a second select voltage having a voltage level higher than a voltage level of the first select voltage.