Memory Selection Circuit for Rapid Image Switching in Display Devices
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Solution Overview
Problem
Conventional display devices with memory-in-pixel (MIP) technology require a full frame period to switch between memories in each pixel, limiting their ability to quickly change images and meet demands for smaller, higher-definition panels.
Innovation Solution
The display device incorporates a memory selection circuit that simultaneously selects from multiple memories in each sub-pixel, allowing for rapid image switching and animation display without the need for individual memory switching circuits in each pixel, and enables writing and reading of sub-pixel data across multiple memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If line sequential scanning is used to control memory switching in each pixel, then the display device can maintain a simple circuit structure, but the image switching speed is limited to one frame period
Solution Approach 1:
The pixel array is divided into multiple independently controllable blocks, with each block having its own memory selection circuit. This segmentation allows different blocks to switch memories simultaneously rather than sequentially, thereby increasing the overall image switching speed while keeping each individual block's circuit structure relatively simple.
Solution Approach 2:
The patent transitions from one-dimensional sequential scanning (line by line across the entire display) to two-dimensional parallel control (independent block control across the display). By organizing memories into multiple blocks that can be controlled independently in parallel, the system achieves faster image switching without proportionally increasing overall circuit complexity.
2Productivity
If multiple memories are included in each pixel with individual switching circuits, then memory switching can be performed rapidly, but the circuit complexity and panel size increase
Solution Approach 1:
Multiple memories within each block share common circuit resources such as data lines, control signals, and parts of the switching mechanism. This merging approach allows rapid memory switching capability while avoiding the need for completely independent switching circuits for each memory, thereby reducing overall circuit complexity and panel size.
Solution Approach 2:
The memory selection circuits are designed with multi-functionality to handle multiple memories within a block using the same control infrastructure. A single selection circuit can rapidly switch between different memories in its block, providing high-speed image change capability without requiring separate dedicated circuits for each memory, thus maintaining manageable circuit complexity.
3Loss of time
If a one-frame period is required to complete memory switching for all pixels, then the display device can use simpler control mechanisms, but it cannot meet demands for quick image changes and animation display
Solution Approach 1:
The display is segmented into multiple blocks that can be controlled independently and simultaneously. This allows memory switching to occur in parallel across different blocks rather than sequentially across the entire display, dramatically reducing the time required for complete image switching from one frame period to a much shorter duration, thereby enabling animation and quick image changes.
Solution Approach 2:
The patent implements preliminary organization of memories into blocks with pre-configured selection circuits, so that when image switching is required, the system can immediately activate the appropriate blocks in parallel without needing to sequentially configure each pixel. This preliminary structuring enables rapid response time for image changes while maintaining relatively simple control mechanisms.
Data Source
AI summary
A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.