Semiconductor Memory Selection Element Dopant Gradient
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in controlling the formation of undesirable interface layers between switching element layers and electrode layers, leading to increased forming voltage and sneak or leakage currents, which deteriorate off-current characteristics.
Innovation Solution
The implementation of a semiconductor memory device with a selection element layer having a dopant concentration profile that decreases from the interface with the first electrode layer to the interface with the second electrode layer, and the use of a barrier layer to suppress the formation of undesirable interface layers, along with a high-energy ion implantation process to control the interface layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional interface between switching element layer and electrode layer is formed without controlled dopant distribution, then manufacturing is simpler, but undesirable interface layers form causing increased forming voltage and leakage currents
Solution Approach 1:
The patent applies local quality by creating a non-uniform dopant concentration profile within the selection element layer. The dopant concentration is highest at the interface with the first electrode layer and decreases toward the interface with the second electrode layer. This localized variation in dopant distribution optimizes the interface region to reduce forming voltage and suppress leakage currents, while maintaining appropriate electrical characteristics in the bulk of the selection element layer.
Solution Approach 2:
The patent employs preliminary action by performing ion implantation to introduce dopants into the selection element layer before final device assembly and operation. This pre-establishment of the dopant concentration profile ensures that the interface layer characteristics are optimized in advance, preventing the formation of undesirable interface layers and reducing forming voltage from the outset rather than requiring corrective measures later.
2Reliability
If high-energy ion implantation is used to control interface layer formation, then forming voltage is reduced and off-current characteristics improve, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by utilizing high-energy ion implantation with specific energy levels and dopant types to precisely control the dopant concentration profile. By adjusting ion implantation parameters (energy, dose, species), the process optimizes the interface region properties to reduce forming voltage and improve off-current characteristics, transforming the manufacturing challenge into a controllable parameter optimization problem.
3Reliability
If uniform dopant distribution is used in selection element layer, then manufacturing is easier, but interface layer formation cannot be controlled leading to increased leakage currents
Solution Approach 1:
The patent applies local quality by creating a non-uniform dopant concentration profile within the selection element layer. The dopant concentration is highest at the interface with the first electrode layer and decreases toward the interface with the second electrode layer. This localized variation in dopant distribution optimizes the interface region to reduce forming voltage and suppress leakage currents, while maintaining appropriate electrical characteristics in the bulk of the selection element layer.
Solution Approach 2:
The patent employs ion implantation, a process analogous to pneumatic and hydraulic principles, to introduce dopants into the selection element layer with precise spatial control. The ion implantation process uses accelerated ion beams to deliver dopants to specific depths and concentrations, creating the desired gradient profile that suppresses leakage currents through controlled interface layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces forming voltage and improves off-current characteristics by controlling the interface layer formation, enhancing the electrical and operational reliability of the memory devices.
Implementation Method 1
performing a first ion implantation process to implant a dopant into a resultant structure of each memory cell including the first electrode layer and the selection element on the substrate
Data Source
AI summary
An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.