Semiconductor Memory Selection Gate Transistor Segmented Structure
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing power consumption and minimizing leak current due to the electrical connection of selection gate transistors, which affects the switching properties and parasitic capacitance, making it difficult to achieve high-speed operation while maintaining withstand voltage.
Innovation Solution
The semiconductor memory device employs a unique structure where the selection gate transistors have a laminated semiconductor layer configuration with a narrower intermediate-layer semiconductor layer and wider source and drain layers, ensuring electrical independence between adjacent transistors, reducing off-current, and optimizing the gate electrode's position to minimize parasitic capacitance and enhance switching properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If selection gate transistors are electrically connected in conventional configuration, then device complexity is reduced, but power consumption increases and leak current rises
Solution Approach 1:
The selection gate transistor is divided into multiple semiconductor layers (first, second, and third semiconductor layers) with different widths. The second semiconductor layer has a narrower width than the first and third layers, creating a segmented structure that reduces overlap with adjacent transistors. This segmentation isolates the electrical fields of adjacent transistors, reducing parasitic capacitance and leak current while maintaining the overall device functionality.
Solution Approach 2:
Different regions of the selection gate transistor are given different local properties through the varying widths of semiconductor layers. The narrowed second layer specifically addresses the region where parasitic capacitance occurs between adjacent transistors, while the wider first and third layers maintain adequate current conduction capability. This local quality adjustment reduces power consumption without compromising overall device performance.
2Productivity
If transistor size is reduced to increase density, then productivity increases, but withstand voltage decreases and leak current increases
Solution Approach 1:
Instead of simply reducing transistor size in two dimensions, the invention utilizes the vertical dimension by creating a multi-layer semiconductor structure. The stacked configuration of first, second, and third semiconductor layers allows the transistor to maintain adequate current conduction area while reducing the lateral footprint. The narrowed second layer specifically reduces parasitic capacitance in the critical region, enabling higher density without sacrificing withstand voltage or increasing leak current.
3Speed
If selection gate transistors operate at high speed, then productivity increases, but power consumption increases due to increased parasitic capacitance
Solution Approach 1:
The segmented semiconductor layer structure with the narrowed second layer reduces parasitic capacitance between adjacent transistors. Lower parasitic capacitance allows for faster charging and discharging of the gate, enabling higher operation speeds. Simultaneously, the reduced capacitance decreases the energy required for switching operations, thereby reducing power consumption while maintaining high-speed performance.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.