3D Nonvolatile Memory Selection Line Leakage Control
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face challenges in controlling leakage current and improving integration density due to the use of selection lines with the same thickness as word lines, leading to complex manufacturing processes and limited integration capabilities.
Innovation Solution
The solution involves forming selection lines and word lines through separate processes, allowing for adjustable channel lengths of selection transistors to control leakage current, and using polysilicon or metal layers for these lines, while gate lines are formed simultaneously in the peripheral region to simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If selection lines have the same thickness as word lines, then manufacturing process is simplified, but leakage current control becomes difficult
Solution Approach 1:
The patent divides the conductive layer formation into separate processes: word lines are formed in one process while selection lines are formed in another process. This segmentation allows independent optimization of each line type's thickness and material properties, enabling leakage current control in selection transistors while maintaining manufacturing feasibility through systematic process design.
Solution Approach 2:
The patent applies different thicknesses and materials to different conductive lines based on their specific functional requirements. Selection lines use thinner conductive layers (e.g., 50-150 nm) compared to word lines to control leakage current, while word lines use thicker layers for strength. This local differentiation of quality parameters optimizes performance for each component's specific role.
2Reliability
If multiple selection transistors are stacked to control leakage current, then leakage current control improves, but manufacturing complexity increases
Solution Approach 1:
Instead of increasing the number of stacked selection transistors, the patent controls leakage current by changing the thickness parameter of the conductive layer in selection lines. By reducing the conductive layer thickness to 50-150 nm, the patent achieves effective leakage current control while maintaining a simpler single-transistor structure, avoiding the manufacturing complexity of multiple stacked transistors.
3Reliability
If contact pad area increases to accommodate more selection transistors, then leakage current control improves, but integration density deteriorates
Solution Approach 1:
The patent controls leakage current by changing the conductive layer thickness parameter rather than increasing contact pad area or stacking more transistors. This approach maintains compact device footprints and preserves integration density while achieving effective leakage current control through optimized material layer dimensions.
Data Source
AI summary
A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. At least one gate line is formed in a peripheral region of the substrate and includes the second conductive layer.