Memory Cell Selection Transistor Layout for Higher Integration Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density due to the size and area requirements of MOS transistors used in word and bit line selection circuits, which hinder the efficient control of current to memory cells and affect performance.
Innovation Solution
The semiconductor memory device design incorporates a peripheral circuit portion with differently sized selection transistors and a cell array portion, utilizing three-dimensional transistors such as FinFETs and MBCFETs to reduce the planar size of transistors and equalize effective gate widths, allowing for a more compact layout without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors are used in word and bit line selection circuits, then current control to memory cells is achieved, but the size and area requirements of these transistors increase, hindering integration density
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional transistors (FinFETs and MBCFETs), utilizing vertical channel structures to achieve higher integration density. The FinFET employs a vertically extending channel with gate electrodes wrapping around three sides, while the MBCFET uses multiple vertically stacked channels, both reducing the planar footprint while maintaining or enhancing current control capability.
Solution Approach 2:
The patent implements nested structures where gate electrodes are positioned to control multiple channel regions. In the MBCFET, inner gate electrodes are surrounded by outer gate electrodes, creating a nested configuration that enables independent control of different channel portions, achieving complex current control functions within a compact volume.
2Area of stationary object
If three-dimensional transistors are used to reduce planar size, then integration density is enhanced, but equalizing effective gate widths becomes more challenging
Solution Approach 1:
The patent applies different gate widths to different regions of the transistor structure. The first and second gate electrodes have different widths to provide asymmetric control over the channel, with wider gates providing stronger control in specific regions. This local differentiation allows precise tuning of current characteristics while maintaining compact dimensions.
Solution Approach 2:
The patent systematically varies gate electrode dimensions, including width, length, and vertical positioning, to optimize transistor performance. By adjusting these geometric parameters, the design achieves equalized effective gate widths across different transistor instances, enabling consistent current control despite the three-dimensional architecture.
Data Source
AI summary
A semiconductor memory device includes: first conductive lines provided on a substrate and extending in a first direction in parallel, each of the first conductive lines including a first end portion and a second end portion that are opposite to each other, the first direction being parallel to a top surface of the substrate; first selection transistors respectively connected to the first end portions of the first conductive lines; and second selection transistors respectively connected to the second end portions of the first conductive lines. Each of the first selection transistors may have a first gate width. Each of the second selection transistors may have a second gate width smaller than the first gate width.