Memory Device Selection Transistors Bit Line Control
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Solution Overview
Problem
Conventional semiconductor memory devices with element isolation regions between memory cell groups face challenges in controlling the potential of all bit line diffusion layers, leading to incorrect operations such as wrong writing, erasure, or reading due to incomplete wiring and potential un drivability of bit line diffusion layers.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with an element isolation region, featuring a specific arrangement of bit line diffusion layers, word lines, selection transistors, and main bit lines, including additional selection word lines and transistors to ensure independent control of bit line diffusion layers, and optionally uses dummy cells for stability and symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If element isolation regions are provided between memory cell groups to divide rewrite units, then rewrite unit size and memory core area are reduced, but wiring control of bit line diffusion layers becomes incomplete leading to incorrect operations
Solution Approach 1:
The memory cell array is segmented into multiple memory cell groups by element isolation regions, with each group containing (8×N) memory cells. This segmentation allows independent control of bit line diffusion layers in each group through dedicated selection transistors, ensuring reliable operation while reducing the overall memory core area required for each rewrite unit.
Solution Approach 2:
Each memory cell group is equipped with its own selection transistors and selection word lines, providing localized control capability. This ensures that bit line diffusion layers within each segmented group can be independently controlled without interference from adjacent groups, maintaining operational reliability while enabling area reduction through segmentation.
2Device complexity
If conventional selection transistor arrangement is used, then device complexity is reduced, but bit line diffusion layers cannot be fully controlled leading to write disturb phenomena
Solution Approach 1:
Selection transistors are configured to serve dual purposes: they select specific memory cells for operation and simultaneously control the potential of bit line diffusion layers to prevent write disturb phenomena. This multi-functional design ensures reliable control without significantly increasing device complexity, as the same transistor structure performs multiple critical functions.
3Reliability
If additional selection transistors and selection word lines are added to control bit line diffusion layers, then operational reliability is improved, but device complexity increases
Solution Approach 1:
The control structure is extended into a new dimension by adding selection word lines that run perpendicular to the main word lines, allowing independent control of bit line diffusion layers without interfering with the existing word line structure. This dimensional addition enables reliable bit line control while maintaining a systematic and organized wiring architecture that minimizes complexity.
Data Source
AI summary
A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8×N) memory cells arranged in a row direction as a unit to be used as a storage region. The number of a plurality of selection word lines is at least eight, and the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines. At least one selection transistor in addition to (8×N) selection transistors are connected in total to the plurality of selection word lines. A plurality of main bit lines includes at least one main bit line in addition to (4×N) main bit lines connected to the common drain of a pair of selection transistors.