Memory Device Selective Bit Line Precharge Optimization
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Solution Overview
Problem
Existing memory devices face challenges in optimizing program operation time and current consumption during memory cell threshold voltage adjustments, as existing methods either lengthen program time or increase current consumption.
Innovation Solution
The memory device employs a selective and non-selective precharge scheme for bit lines based on the number of verify operations, using a page buffer controller to adjust precharge signals, optimizing the number of verify operations in each loop to balance program time and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all bit lines are precharged during every verify operation, then sensing accuracy is improved, but current consumption increases
Solution Approach 1:
The patent applies partial precharge by selectively precharging only a subset of bit lines (first bit lines) during initial verify operations rather than precharging all bit lines. This partial action reduces current consumption while maintaining sufficient sensing accuracy for the verification process.
Solution Approach 2:
The patent dynamically adjusts the precharge strategy based on the verify operation count. When the number of verify operations exceeds a threshold, the system transitions to precharging all bit lines (second bit lines) to ensure adequate sensing accuracy, thereby adapting the behavior to current operational conditions.
2Use of energy by moving object
If selective precharge is used for bit lines, then current consumption is reduced, but program operation time increases
Solution Approach 1:
The patent implements periodic verification where verify operations are performed at regular intervals during the program operation. By incorporating verify operations periodically rather than continuously, the system reduces the total time spent on verification while maintaining the benefits of selective precharge for current consumption reduction.
3Reliability
If multiple verify operations are performed in each loop, then programming reliability is improved, but program operation time increases
Solution Approach 1:
The patent incorporates verify operations that provide feedback on the programming status of memory cells. By performing verify operations to check whether threshold voltages have reached target levels, the system ensures reliable programming while optimizing the number of verification cycles to minimize time consumption.
Data Source
AI summary
Provided herein may be a memory device and a method of operating the memory device. The memory device may include a memory block coupled to bit lines and word lines, a voltage generator configured to apply at least one of a program voltage or a verify voltage to a word line selected from among the word lines, page buffers configured to precharge less than all or all of the bit lines during a verify operation performed on the memory cells, an operation logic configured to output verify information related to a verify operation performed during a program operation in response to a command, and a page buffer controller configured to output page buffer control signals so that the less than all of the bit lines are selectively precharged or the all of the bit lines are precharged depending on the verify information.