Non-Volatile Memory Selective Erasing Control Voltage Provider
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Solution Overview
Problem
Existing flash memory apparatuses require simultaneous erasure of all memory sectors in the same well, limiting the capability for small size memory sector erasure and increasing chip size due to the need for additional sector selectors and wells.
Innovation Solution
A non-volatile memory apparatus with a control voltage provider that differentiates control line signals for selected and un-selected memory sectors within the same well, allowing for selective erasure by applying erase and un-erase control voltages to respective memory sectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all memory sectors in the same well are erased simultaneously, then the erasing operation is simple to implement, but the capability for small size memory sector erasure is limited
Solution Approach 1:
The patent divides the memory array into multiple independently selectable memory sectors (e.g., MS0, MS1, MS2, MS3) within the same well. Each sector can be individually selected for erasure through separate select lines (S0, S1, S2, S3), enabling selective erasure of small size memory sectors without requiring additional wells or complex isolation structures. This segmentation allows the system to erase only the required portion of memory while maintaining operational simplicity.
2Adaptability or versatility
If additional sector selectors and wells are increased for small size memory sector erasure, then the erasure selectivity is improved, but the chip size is increased
Solution Approach 1:
The patent merges multiple memory sectors (MS0, MS1, MS2, MS3) into a single well structure, eliminating the need for separate wells for each sector. By sharing the common well infrastructure and using individual select lines to control erasure operations, the design achieves high sector selection flexibility while minimizing chip area. This approach consolidates resources that would otherwise be duplicated across multiple wells.
Solution Approach 2:
The well structure is designed to serve multiple functions: it can simultaneously accommodate multiple memory sectors and support both read and erase operations across different sectors. The select lines (S0-S3) provide universal control capability, allowing any combination of sectors to be selected for erasure without requiring dedicated control circuits for each sector, thereby reducing overall chip size while maintaining flexibility.
3Reliability
If isolated transistors are used for sector separation, then the sector isolation is improved, but the chip size is increased
Solution Approach 1:
The patent introduces select lines (S0, S1, S2, S3) as intermediary control signals that mediate between the control logic and memory sectors. These select lines provide electrical isolation and control without requiring physical isolation structures like trench oxides or guard rings between sectors. The intermediary control mechanism achieves reliable sector separation while minimizing the area occupied by isolation structures.
Data Source
AI summary
The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.