3D Non-Volatile Memory Selective Erase Inhibition
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Solution Overview
Problem
In 3D stacked non-volatile memory devices, the existing erase operations face challenges such as deep-erase phenomena due to strong erase voltages, which can lead to over-erasure of lower data states and degradation, and are limited by gate-induced drain leakage (GIDL) current, affecting the efficiency and reliability of multi-level cell (MLC) implementation in BiCS technology.
Innovation Solution
The solution involves selectively inhibiting subsets of memory cells during the erase operation by controlling voltages on word lines, bit lines, and select gate lines, allowing for independent management of erase processes, and adjusting the GIDL current by stepping up the intermediate voltage (Vgidl) in erase iterations to optimize erase efficiency and prevent over-erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If strong erase voltages are applied to improve erase speed, then erase efficiency is improved, but deep-erase phenomena occur causing over-erasure of lower data states and degradation
Solution Approach 1:
The patent segments the memory cells into different subsets based on their data states and selectively applies erase operations to each subset. This allows strong erase voltages to be applied only to cells that need erasing, while protecting cells in lower data states from over-erasure, thus resolving the contradiction between erase speed and data integrity
Solution Approach 2:
The patent applies different erase voltage levels to different subsets of memory cells based on their specific requirements. Cells in higher data states receive stronger erase voltages while cells in lower data states receive reduced voltages, ensuring each cell subset receives appropriate erase strength without causing damage
2Productivity
If gate-induced drain leakage current is increased to improve erase efficiency, then erase speed is improved, but reliability and control precision deteriorate
Solution Approach 1:
The patent dynamically adjusts the gate-induced drain leakage current during the erase operation by applying voltage steps. The GIDL current is increased only when necessary to overcome erasure barriers, and reduced when cells are successfully erased, allowing efficient erasure while maintaining precise control and preventing excessive current that would harm reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces over-erasure issues, minimizes degradation, and enhances the reliability of multi-level cell operations by allowing precise control over the erase process, improving the endurance and performance of 3D stacked non-volatile memory devices.
Implementation Method 1
gate-induced drain leakage (GIDL) current
Data Source
AI summary
An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.