Non-Volatile Memory Selective Erasing Floating Gate Coupling
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Solution Overview
Problem
In multi-state non-volatile semiconductor memory devices, floating gate to floating gate coupling leads to erroneous readings due to shifts in apparent charge, especially in memory cells programmed at different times or concurrently, causing cells to be shifted from allowed to forbidden threshold voltage ranges, which complicates the implementation of multi-state memories as cells shrink in size.
Innovation Solution
A method for selectively erasing or adjusting memory cells that are supposed to remain erased but appear to have been changed due to coupling, without intentionally erasing or adjusting properly programmed data, by performing multi-pass programming and selective re-erasing processes to maintain accurate threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-state memory devices are implemented with narrower threshold voltage ranges, then storage density is improved, but floating gate coupling causes more erroneous readings
Solution Approach 1:
The patent applies preliminary action by performing a selective erase operation on a first group of memory cells before programming operations. This pre-erasure of potentially coupled cells prevents floating gate coupling from causing erroneous readings during subsequent programming and reading operations, thereby maintaining reading accuracy while enabling multi-state storage.
2Productivity
If memory cells are programmed concurrently to different states, then programming efficiency is improved, but coupling effects cause cells to shift from allowed to forbidden threshold voltage ranges
Solution Approach 1:
The patent segments the memory array into different groups of memory cells based on their programming states. A first group of memory cells is selectively erased while a second group is programmed, allowing concurrent operations on different segments without interference. This segmentation prevents coupling effects from causing threshold voltage shifts that would move cells into forbidden ranges.
Solution Approach 2:
The patent applies local quality by performing selective erase operations on specific groups of memory cells rather than erasing the entire array. This localized approach ensures that only the necessary cells are affected, maintaining precise threshold voltage control for cells that should remain in their programmed states while improving overall programming efficiency.
3Reliability
If selective erase operations are performed to correct coupling errors, then reading accuracy is improved, but device complexity increases
Solution Approach 1:
The patent performs selective erase operations as a preliminary step before programming operations. By proactively erasing potentially coupled cells before they can cause reading errors, the system maintains high reading accuracy without requiring complex error detection and correction procedures during normal operation, thus limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that memory cells remain accurately programmed and erased, reducing errors and maintaining the integrity of threshold voltage distributions, thereby enhancing the reliability and precision of multi-state memory operations.
Implementation Method 1
Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised
Implementation Method 2
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates
Data Source
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AI summary
A non- volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.