Nonvolatile Memory Device Selective Area Error Restriction

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Solution Overview

Problem

Nonvolatile memory devices face inefficiencies when errors occur in memory areas, leading to unnecessary disabling of entire blocks, which reduces available memory capacity and user efficiency.

Innovation Solution

Implementing a control method with first and second flag storage units to impose usage restrictions on memory areas, allowing selective disabling of faulty components while maintaining functionality of healthy parts, thereby optimizing memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an error is detected in a part of memory areas, the entire memory block is disabled to ensure reliability, then reliability is improved, but memory capacity is reduced

Engineering Contradiction:

Improvememory reliabilityVSAvoidmemory capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The memory block is divided into multiple memory areas, each with its own error detection and flag storage unit. When an error is detected in one area, only that specific area is restricted while other areas remain functional. This segmentation allows the system to maintain reliability by isolating errors while preserving memory capacity by keeping non-affected areas operational.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by implementing usage restrictions only in the specific memory area where an error is detected, rather than disabling the entire block. Each memory area has its own flag storage unit that independently tracks error status, allowing healthy areas to continue operating at full capacity while faulty areas are selectively restricted.

Inventive Principle:

Principle #3Local quality

2Reliability

If the entire memory block is disabled when an error occurs, then reliability is improved, but productivity is reduced

Engineering Contradiction:

Improvememory reliabilityVSAvoidmemory utilization efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The memory block is segmented into multiple independent memory areas with separate error tracking. This allows the system to maintain high productivity by keeping error-free areas operational while isolating and restricting only the faulty segments, thereby maintaining overall memory utilization efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent ensures continuity of useful action by allowing memory operations to continue in non-affected areas even when errors are detected in specific regions. The selective restriction mechanism enables ongoing memory utilization in healthy areas, maintaining productivity while ensuring reliability through targeted error management.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11461044B2Nonvolatile memory device controlling partical usage restriction for memory cell array

Publication Date: 2022.10.04 KIOXIA CORP

AI summary

According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.