Fin-Structured Memory Array Selectors for Compact MRAM Writing
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Solution Overview
Problem
As semiconductor devices shrink, memory arrays face challenges with reduced layout area and increased bit error rates due to low driving current, necessitating improved write performance and reduced layout area for memory units like MRAM.
Innovation Solution
The memory array design incorporates selectors with two pairs of fin structures and a gate structure that crosses these fin structures, along with a staggered pattern of conductive vias, to enhance driving current and reduce layout area, thereby improving write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory devices are continuously shrunk to reduce layout area, then layout area is reduced, but driving current decreases and bit error rate increases
Solution Approach 1:
The selector is divided into two pairs of fin structures instead of a single structure, allowing the driving current to be distributed across multiple fins while maintaining a compact layout. This segmentation enables the memory unit to achieve sufficient driving current despite the overall size reduction.
Solution Approach 2:
Multiple fin structures are merged into a single selector unit with shared gate control, creating a compact configuration that delivers high driving current. The combined fins work together to provide the necessary current while occupying minimal layout area.
2Area of stationary object
If memory devices are continuously shrunk to reduce layout area, then layout area is reduced, but write performance deteriorates
Solution Approach 1:
The selector is divided into two pairs of fin structures instead of a single structure, allowing the driving current to be distributed across multiple fins while maintaining a compact layout. This segmentation enables the memory unit to achieve sufficient driving current despite the overall size reduction.
Solution Approach 2:
Multiple fin structures are merged into a single selector unit with shared gate control, creating a compact configuration that delivers high driving current. The combined fins work together to provide the necessary current while occupying minimal layout area.
3Ease of manufacture
If conventional selector structures are used in shrunk memory devices, then manufacturing is simpler, but driving current is insufficient
Solution Approach 1:
The fin structures are configured to dynamically respond to gate voltage changes, optimizing the channel width and driving current. The multiple fins provide increased total channel width while maintaining compatibility with standard fabrication processes.
Solution Approach 2:
The selector structure transitions from a conventional single-fin design to a multi-fin configuration, changing the physical parameters such as total channel width and surface area. This parameter change increases driving current while the fabrication process remains substantially the same.
Data Source
AI summary
A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.