Semiconductor Memory Self Refresh Clock Phase Detection
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Solution Overview
Problem
Conventional semiconductor memory devices face errors and design challenges in the self refresh mode due to synchronization issues with external clock signals, leading to erroneous operations and high power consumption.
Innovation Solution
A sensing signal generating circuit that buffers and compares positive and negative external clock signals to determine phase alignment, generating a self refresh enable signal for activating or deactivating the self refresh mode, and includes a filtering unit to remove glitches, allowing for precise control of the self refresh mode entry and exit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the self refresh mode entry and exit is controlled by external clock signal CLK and auto refresh command AREF synchronized with the clock signal, then the self refresh operation can be executed according to semiconductor standards, but erroneous operations can occur when the combination of clock enable signal and auto refresh command has errors or margins
Solution Approach 1:
The patent extracts the clock signal phase relationship detection function from the complex control signal combination logic. By detecting whether the external clock signal is in the rising edge or falling edge phase, the system simplifies the control mechanism and eliminates the need for complex synchronized command combinations, thereby improving reliability while reducing control complexity
Solution Approach 2:
The patent changes the control parameter from complex signal combinations (clock enable signal + auto refresh command) to a simple phase detection parameter (rising edge vs. falling edge of external clock signal). This parameter transformation simplifies the control logic and reduces the probability of erroneous operations
2Reliability
If the external clock signal CLK is used to control self refresh mode entry and exit, then the operation follows standard synchronization protocols, but there is a high probability of error in activating the internal clock signal after the clock enable signal goes high during self refresh exit mode
Solution Approach 1:
The patent performs preliminary phase detection of the external clock signal before activating the internal clock signal during self refresh exit. By detecting the clock phase in advance and generating the self refresh exit signal accordingly, the system ensures reliable internal clock activation without complex circuitry
Solution Approach 2:
The patent introduces a phase detection circuit as an intermediary between the external clock signal and the internal clock signal activation. This intermediary detects the clock phase and generates appropriate control signals, simplifying the overall clock activation circuit while improving reliability
3Reliability
If the self refresh mode uses row address signals from a counter and changes output signals for a predetermined period, then cell restoration can be achieved, but the operation duration and timing precision are limited
Solution Approach 1:
The patent uses the external clock signal phase as feedback to control the self refresh operation timing. By monitoring the clock phase (rising or falling edge), the system dynamically adjusts the refresh timing, improving both restoration reliability and timing flexibility compared to fixed predetermined periods
Data Source
AI summary
The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal.