Memory Self-Refresh Power Gating via Controller Context Preservation
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Solution Overview
Problem
Existing memory technologies, such as DRAM, often enter a low power state by clock gating but not power gating the physical layer (PHY), due to the requirement of reconfiguring the memory controller, which can necessitate a system reboot.
Innovation Solution
The implementation of a memory self-refresh power gating state that preserves the context of the memory controller by saving it to a non-volatile memory device or by supplying a retention supply voltage, allowing the physical layer to be power gated in addition to clock gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to the physical layer (PHY) of memory, then power consumption is reduced, but the memory controller requires reconfiguration which can necessitate a system reboot
Solution Approach 1:
The memory system is segmented into two distinct power domains: the physical layer (PHY) which can be fully powered down, and the memory controller which maintains a reduced power state with retention voltage. This segmentation allows the PHY to be power-gated independently without requiring full system reboot, while the memory controller retains enough power to maintain context and configuration state.
Solution Approach 2:
The context of the memory controller is preserved in advance by maintaining a retention supply voltage to its registers before the PHY is power-gated. This preliminary action of preserving controller state allows the system to transition to a low-power state without losing configuration information, eliminating the need for system reboot when exiting the low-power state.
2Ease of manufacture
If only clock gating is used in low power state, then the system remains simple to implement, but power consumption reduction is limited
Solution Approach 1:
The system implements dynamic power management with multiple power states: a full-power state, a self-refresh state with clock gating only, and a deeper low-power state with PHY power gating. The system can dynamically transition between these states based on workload requirements, providing both implementation simplicity for basic states and enhanced power savings when the deeper state is utilized.
3Loss of energy
If the memory enters a deep low power state with PHY power gating, then power consumption is reduced, but entry and exit latency may increase
Solution Approach 1:
The patent replaces the traditional mechanical approach of complete system shutdown with an electrical solution using retention voltage. By substituting the retention voltage mechanism for full controller power-down, the system achieves PHY power gating with minimal latency impact, as the controller context is electrically maintained rather than mechanically reset.
Data Source
AI summary
The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.