Embedded Memory Self Repair via Error Classification
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Solution Overview
Problem
Advanced semiconductor technology applications with large embedded memories face significant reliability risks due to higher intrinsic defects and lower voltage margins, leading to increased memory hard failure rates over time, necessitating self-repair techniques for marginal and defective memory cells to optimize network availability.
Innovation Solution
A memory control device is implemented with a content addressable memory component and a back-up memory component to detect, classify, and correct bit sequence errors by comparing error addresses to a database, classifying errors as soft or hard, and using the back-up memory to replace hard errors, thereby preventing repeated errors and maintaining network availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large embedded memories are used in advanced semiconductor technology applications, then memory density and bandwidth are improved, but reliability deteriorates due to higher intrinsic defects and lower voltage margins
Solution Approach 1:
The memory system is segmented into functional components: a main memory array, an error detection unit, an address database, and a back-up memory. This segmentation allows the system to isolate and handle errors in specific memory locations without affecting the entire memory system, thereby maintaining reliability while preserving high density.
Solution Approach 2:
The system performs preliminary error detection and classification before data access operations. By proactively identifying and classifying errors using the address database and content addressable memory, the system prevents defective data from being accessed, maintaining reliability while the high-density memory remains fully utilized.
2Reliability
If self-repair techniques are implemented to correct memory errors, then reliability is improved, but device complexity increases due to additional memory components and error handling logic
Solution Approach 1:
A content addressable memory component serves as an intermediary between the main memory and the error correction logic. This intermediary efficiently maps error addresses to back-up data locations, simplifying the error handling process while maintaining high reliability through automated error correction.
Solution Approach 2:
The memory system implements self-service through automated error detection, classification, and correction mechanisms. The error detection unit continuously monitors memory integrity, and the system automatically retrieves back-up data when errors are detected, eliminating the need for external intervention and reducing operational complexity.
3Productivity
If error classification and correction mechanisms are added to distinguish soft and hard errors, then memory usage optimization is improved, but manufacturing complexity increases
Solution Approach 1:
The error handling system is segmented into distinct functional blocks: error detection logic, address comparison units, classification mechanisms, and back-up memory management. This modular segmentation enables independent optimization of each component during manufacturing, reducing overall manufacturing complexity while achieving sophisticated error classification and correction capabilities.
Data Source
AI summary
Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.