Memory Self-Test Signaling for Single-Bit Error Visibility
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Solution Overview
Problem
Existing memory devices fail to inform host devices about single-bit errors (SBEs) detected during built-in self-tests, especially in safety-critical applications like automotive systems, as on-die error-correcting codes mask these errors, leading to potential reliability and safety issues.
Innovation Solution
The memory device performs a built-in self-test (MBIST) with on-die error correction disabled, identifies single-bit errors, and transmits an indication of the error count to the host device, allowing it to take corrective actions based on predefined thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die error-correcting codes are enabled during self-test, then error masking and data integrity are improved, but single-bit error detection capability deteriorates
Solution Approach 1:
The patent dynamically adjusts the error correction status based on test requirements. During MBIST, error correction is disabled to enable precise single-bit error detection. During normal operation, error correction is enabled to maintain data integrity. This dynamic switching resolves the contradiction between detection precision and reliability.
Solution Approach 2:
The patent segments the operational modes into distinct phases: self-test mode with error correction disabled for precise error detection, and normal operation mode with error correction enabled for data integrity. This segmentation allows each mode to optimize for its specific function without compromise.
2Reliability
If single-bit error indication is implemented, then host device awareness and safety are improved, but device complexity increases
Solution Approach 1:
The patent introduces a mode register as an intermediary between the memory device and host device. The mode register stores error status information that the host can read without requiring complex real-time communication mechanisms. This simple register-based approach provides error indication while minimizing added complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device writes error status to a mode register, and the host device reads this register to obtain error information. This structured feedback loop provides reliable error indication while maintaining simplicity through standardized read/write operations.
3Measurement precision
If built-in self-test is performed with error correction disabled, then single-bit error identification is improved, but test reliability deteriorates
Solution Approach 1:
The patent segments the testing process into phases: first performing MBIST with error correction disabled to precisely identify single-bit errors, then performing additional tests with error correction enabled to verify test reliability. This segmentation allows each phase to optimize for its specific objective.
Solution Approach 2:
The patent performs preliminary error identification using MBIST with error correction disabled, then uses this information to guide subsequent testing with error correction enabled. This preliminary action allows the system to focus resources on verifying specific error conditions rather than generic testing.
Data Source
AI summary
Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.