Memory Sense Amplifier Arrays With Parallel Mismatch Compensation
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Solution Overview
Problem
Sense amplifiers in memories face challenges in accurately sensing and amplifying small voltage differences between bit lines due to manufacturing mismatches between PMOS and NMOS transistors, leading to offset voltages that hinder accurate data sensing and amplification.
Innovation Solution
Implement a memory system with a normal cell array and redundancy cell array, each equipped with respective sense amplifier arrays, and a repair determination circuit to manage mismatch compensation operations, allowing for parallel initiation of mismatch compensation in both arrays before determining access, thereby reducing mismatch effects and minimizing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If mismatch compensation operation is performed sequentially after repair determination, then device complexity is reduced, but access time increases and productivity decreases
Solution Approach 1:
The patent initiates mismatch compensation operations in both normal and redundancy sense amplifier arrays simultaneously with the active command, before the repair determination circuit completes its evaluation. This preliminary action allows the compensation to begin early, reducing the overall access time while the control circuit subsequently deactivates the redundancy array if not needed.
Solution Approach 2:
The system dynamically adjusts the operation of sense amplifier arrays based on real-time repair determination. The control circuit monitors the repair evaluation outcome and dynamically deactivates the redundancy sense amplifier array when normal cells are accessible, optimizing resource utilization and reducing unnecessary power consumption while maintaining fast access paths.
2Use of energy by moving object
If mismatch compensation is performed in only one sense amplifier array, then power consumption is reduced, but sensing accuracy deteriorates due to uncompensated transistor mismatches
Solution Approach 1:
The patent applies mismatch compensation locally to the specific sense amplifier array that will be used for the current operation. By determining which array (normal or redundancy) will be accessed and only compensating that array, the system achieves accurate sensing with minimized power consumption, avoiding unnecessary compensation operations in the unused array.
Solution Approach 2:
The system changes the operational parameters of the sense amplifier arrays dynamically - enabling compensation only for the active array based on repair determination results. This parameter change approach ensures sensing accuracy is maintained for the accessed array while reducing overall power consumption by leaving the other array in a low-power state.
3Reliability
If redundancy sense amplifier array is kept active for potential compensation, then sensing accuracy is maintained, but device complexity and power consumption increase
Solution Approach 1:
The system performs preliminary mismatch compensation in both arrays simultaneously with the active command, ensuring that whichever array is ultimately selected will have its compensation already completed. This preliminary action guarantees sensing reliability without requiring the redundancy array to remain actively compensated throughout the entire access cycle.
Solution Approach 2:
The control circuit dynamically manages the state of redundancy sense amplifier arrays based on repair determination outcomes. When normal cells are accessible, the redundancy array is deactivated after its brief preliminary compensation, reducing complexity and power consumption while maintaining reliability through the pre-performed compensation.
Data Source
AI summary
An operation method of a memory may include receiving a first active command and a first row address; starting a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundancy sense amplifier array for a redundancy cell array corresponding to the normal cell array; determining to access the normal cell array based on the first row address and repair information; deactivating the redundancy sense amplifier array for the redundancy cell array in response to a determination that the normal cell array is to be accessed; activating a word line of the normal cell array corresponding to the first row address; and sensing and amplifying, by the sense amplifier array for the normal cell array, data of memory cells corresponding to the activated word line.