Memory Device Bit Line Sense Amplifier Offset Compensation
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Solution Overview
Problem
The bit line sense amplifier in semiconductor memory devices experiences reduced effective sensing margin due to coupling noise and offset noise, leading to inadequate voltage variation sensing, especially as memory devices become more integrated and miniaturized.
Innovation Solution
The proposed memory device incorporates a bit line sense amplifier with a charge transfer transistor, an offset transistor, and a pre-charging transistor, along with a global connection controller, to compensate for threshold voltage offsets and improve sensing performance by equalizing voltages and connecting nodes during offset removal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device is miniaturized and integrated to improve functionality and speed, then the integration density increases, but the effective sensing margin of the bit line sense amplifier is reduced due to coupling noise and offset noise
Solution Approach 1:
The patent applies preliminary action by performing offset removal before the sensing operation. The bit line sense amplifier undergoes an offset removal phase where the offset transistor equalizes the voltage levels on the bit line and complementary bit line, compensating for threshold voltage offsets before actual data sensing occurs. This preliminary calibration ensures accurate sensing despite miniaturization effects.
Solution Approach 2:
The patent introduces an offset transistor as an intermediary element to compensate for threshold voltage offsets. The offset transistor is configured to equalize the voltage levels on the bit line and complementary bit line during the offset removal phase, acting as a mediator to cancel out the harmful offset effects that arise from device miniaturization and integration.
2Use of energy by moving object
If the bit line sense amplifier operates with lower voltage variations to improve energy efficiency, then energy consumption decreases, but the amplifier cannot sense the voltage variation accurately
Solution Approach 1:
The patent performs preliminary offset removal to establish accurate baseline voltage levels before sensing operations. By equalizing the bit line and complementary bit line voltages in advance, the system can detect smaller voltage variations with higher accuracy even when operating at lower voltage swings, thus maintaining sensing precision while reducing energy consumption.
Solution Approach 2:
The patent dynamically changes the operational parameters of the bit line sense amplifier by switching between offset removal mode and sensing mode. During offset removal, the offset transistor is activated to equalize voltages; during sensing, the amplifier operates with optimized voltage levels. This parameter switching enables accurate sensing at lower voltage variations, improving energy efficiency without sacrificing measurement precision.
Data Source
AI summary
A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.