Semiconductor Memory Sense Amplifier Overlapping Signals
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high data output speeds while ensuring data stability, particularly in non-volatile memory devices like flash memories, which are used in portable electronic devices and storage solutions.
Innovation Solution
The semiconductor memory device incorporates a memory cell unit with multiple memory banks and sense amplifier groups, where the control logic block generates overlapping column selection signals to transfer data between memory banks and sense amplifiers, allowing for simultaneous data sensing and output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices are used to retain data without power, then data stability is improved, but data input/output speed deteriorates
Solution Approach 1:
The memory system is divided into multiple memory banks (first memory bank, second memory bank) that can operate independently and simultaneously. This segmentation allows parallel data access operations, where different banks can be sensed and transferred at the same time, thereby increasing overall data input/output speed while maintaining the reliability benefits of non-volatile memory
2Productivity
If data transfer operations are performed sequentially in non-overlapping time periods, then operation simplicity is maintained, but data output speed deteriorates
Solution Approach 1:
The control logic block is designed to generate overlapping column selection signals in advance, where the timing of signal generation is pre-coordinated to ensure that sensing operations on different memory banks occur simultaneously. This preliminary coordination of timing allows parallel operations without requiring complex real-time arbitration logic
Solution Approach 2:
By making the active sections of column selection signals overlap, the system ensures continuous useful action during data sensing and transfer operations. Multiple data transfer operations proceed simultaneously without idle time between them, maximizing productivity while the control logic manages the overlapping timings
Data Source
AI summary
A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.