Semiconductor Memory Sense Amplifier Reference Current Stabilization
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Solution Overview
Problem
In resistance change memory devices, accurate determination of defective bits is challenging due to fluctuations in the reference current, which complicates the identification of abnormal resistance states in memory cells.
Innovation Solution
A semiconductor memory device incorporating a sense amplifier that compares currents through two nodes, with a connection control circuit that switches between connecting a memory cell and a reference cell during regular operation and a reference voltage terminal during testing, allowing for a stable reference current in test mode to accurately determine defective bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a differential amplification scheme using a reference cell is adopted to expand the operating range by compensating for resistance changes, then the operating range is expanded, but the reference current fluctuates making accurate determination of defective bits difficult
Solution Approach 1:
The patent implements a dynamic switching mechanism between two operational modes: test mode and read mode. In test mode, the reference cell is disconnected and a stable reference voltage is applied to the sense amplifier input, enabling precise defective bit determination. In read mode, the reference cell is connected to provide differential amplification for expanded operating range. This dynamic reconfiguration allows the system to switch between precision measurement and adaptive operation as needed.
Solution Approach 2:
The patent divides the operational functionality into separate modes with distinct circuit configurations. The sense amplifier circuit is segmented to handle different functions: in test mode it compares current against a stable reference, while in read mode it performs differential amplification. This segmentation allows each mode to optimize for its specific purpose without compromising the other.
2Reliability
If a reference cell is used to compensate for resistance fluctuations, then resistance changes due to power supply voltage and temperature fluctuations are compensated, but the reference current fluctuates preventing accurate defective bit specification
Solution Approach 1:
The system dynamically switches between using a reference cell for compensation during normal operation and using a stable reference voltage for precise measurement during testing. This dynamic selection allows the system to benefit from both compensation capability and measurement precision at different times.
Solution Approach 2:
The patent introduces a connection control circuit as an intermediary that selectively connects either the reference cell or the reference voltage terminal to the sense amplifier. This intermediary component enables the system to transition between compensation mode and precise measurement mode, resolving the conflict between reliability and measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables precise identification of defective bits by stabilizing the reference current during testing, improving the accuracy of bit determination and expanding the operating range of resistance change memory devices.
Implementation Method 1
a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other
Data Source
AI summary
A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.