Memory Sense Amplifier Timing Control for Noise Prevention
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Solution Overview
Problem
High-speed memory devices face challenges in preventing errors due to clock signal noise during sensing intervals, which is exacerbated by varying operating frequencies and power supply voltages, making it difficult to design memory devices immune to noise.
Innovation Solution
A memory device with a sense amplifier that uses two sources of timing signals, one with indeterminate timing relative to the clock signal and another synchronized with the clock signal, to define pre-charge and sensing intervals, ensuring that clock signal transitions occur outside the sensing interval, thereby preventing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal period is reduced to increase operating speed, then productivity is improved, but noise interference during sensing intervals increases causing errors
Solution Approach 1:
The patent implements dynamic timing adjustment by providing multiple timing signal sources (first and second timing signals) that can be selectively activated based on operating conditions. The system dynamically switches between different timing schemes to optimize both speed and reliability across varying clock frequencies, rather than using a fixed timing approach
Solution Approach 2:
The patent changes the timing parameters of the sensing interval relative to the clock signal. By adjusting when the sensing interval occurs within the clock cycle and using different timing signal sources, the system optimizes the relationship between clock frequency and sensing operations to prevent noise interference while maintaining high-speed operation
2Use of energy by moving object
If power supply voltage is reduced to achieve low-power operation, then energy consumption is decreased, but noise impact becomes more severe degrading reliability
Solution Approach 1:
The timing system dynamically adapts to different power supply voltage levels by selecting appropriate timing signal sources. When operating at lower voltages, the system can switch to timing schemes that provide greater noise margins or adjust sensing intervals to avoid problematic clock transitions, maintaining reliability across the power range
3Device complexity
If fixed timing signals are used for sensing intervals, then device complexity is reduced, but adaptability to different operating frequencies is limited
Solution Approach 1:
The patent implements multi-functionality by designing the timing signal generation system to serve multiple operating frequencies and conditions through different timing signal sources. The first and second timing signals can be selectively activated based on the operating frequency range, allowing a single system to adapt universally across specified frequency ranges without requiring completely different timing circuits for each frequency
Data Source
AI summary
A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the signal from the sense amplifier. A first source of timing signals generates a first timing signal in response to an enable signal which is asynchronous relative to the clock signal. A second source of timing signals generates a second timing signal based on the clock signal. A switch selects one of the first and second timing signals at the timing signals for use to define pre-charge and sensing intervals for the sense amplifier. The first source of timing signals is selected during an interval of time corresponding to a clock latency, so that the timing signals define a sensing interval where transitions in the clock signal are outside of the sensing interval.