Memory Sense Amplifier Feedback Loop for Low-Power State Detection
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with high power consumption and inaccurate data state determination due to large voltage potential swings and charge pumping, which affect the net quantity of majority charge carriers in the electrically floating body region.
Innovation Solution
The semiconductor memory device employs data sense amplifier circuitry with current or voltage sensing techniques to compare the current or voltage from a selected memory cell to a reference signal, allowing for accurate determination of data states without significant power consumption, using a two-step or one-step write operation and incorporating multiplexers to couple bit lines to data sense amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reading techniques are used to sense memory cell data states, then data state determination is performed, but power consumption increases and voltage potential swings cause disturbance to unselected memory cells
Solution Approach 1:
The sensing operation is divided into two distinct phases: a first sensing operation that reads data from a first memory cell, and a second sensing operation that reads data from a second memory cell. This segmentation allows the system to manage power consumption and voltage swings by processing memory cells in separate, controlled steps rather than simultaneously, thereby reducing disturbance to unselected cells while maintaining accurate data state determination.
Solution Approach 2:
The patent employs periodic sensing operations where voltage potentials are applied in a sequential, periodic manner to different memory cells. By alternating between sensing operations on different cells and applying compensating voltage potentials during intervals, the system reduces net voltage swings and minimizes disturbance to unselected cells while maintaining measurement precision.
2Ease of manufacture
If pulsing between positive and negative gate biases is applied during read and write operations, then writing operations are performed, but the net quantity of majority charge carriers in the electrically floating body region is reduced
Solution Approach 1:
The patent applies a compensating voltage potential to the well region in advance of or during the sensing operation to counteract the harmful effect of charge pumping. This preliminary anti-action prevents the reduction of majority charge carriers in the electrically floating body region that would otherwise result from pulsing between positive and negative gate biases during write operations, thereby maintaining data state accuracy.
Solution Approach 2:
The patent converts the harmful effect of charge pumping (which reduces majority charge carriers) into a beneficial compensating action. By deliberately applying a compensating voltage potential that counteracts charge pumping, the system transforms the potential harm into a controlled correction mechanism, ensuring accurate data state determination while maintaining write operation capability.
3Object-generated harmful factors
If a bias signal below threshold voltage potential is applied to the gate, then channel formation is eliminated, but trapped minority charge carriers combine with majority charge carriers reducing net quantity
Solution Approach 1:
The compensating voltage potential applied to the well region serves as a preliminary anti-action that prevents the combination of trapped minority charge carriers with majority charge carriers. By establishing this compensating field before or during the sub-threshold gate biasing operation, the system counteracts charge pumping and maintains the net quantity of majority charge carriers in the electrically floating body region.
4Productivity
If large voltage potential swings are applied during read and write operations, then data state changes are achieved, but disturbance to unselected memory cells increases
Solution Approach 1:
The patent segments the application of voltage potentials to different memory cells in time, performing sensing operations on one cell at a time. This temporal segmentation reduces the simultaneous voltage swings affecting multiple cells, thereby minimizing disturbance to unselected memory cells while maintaining operational efficiency through systematic processing.
Solution Approach 2:
The well region voltage potential acts as an intermediary that mediates between the gate bias signals and the memory cell operations. By controlling the well region potential, the system can apply necessary voltage swings for read and write operations while filtering out harmful effects on unselected cells, thus maintaining productivity without causing disturbance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances the accuracy of data state determination by minimizing voltage swings and charge pumping, thereby improving the reliability of reading and writing operations in semiconductor memory devices.
Implementation Method 1
sensing an amount of current provided/generated by/in the electrically floating body region of the memory cell in response to the application of the source/drain region and gate bias signals
Data Source
AI summary
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.