Sequential Memory Sensing Without Access Line Deactivation
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Solution Overview
Problem
Conventional memory operations often result in increased power consumption and extended memory operation times due to poorly controlled signals, which can lead to inefficient data access and storage in memory devices like flash memory.
Innovation Solution
The implementation of a memory device architecture that includes buffer circuitry and specific signal control methods, such as maintaining signal levels during operations, to improve power efficiency and reduce memory operation time by sensing data lines without precharging between sensing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If signals are deactivated between sensing stages in conventional memory operations, then power consumption is reduced, but memory operation time increases due to repeated signal activation and precharging
Solution Approach 1:
The patent maintains access line signals in an activated state continuously across multiple sensing stages rather than deactivating and reactivating them. This continuous signal presence eliminates the time penalty of repeated activation while the selective maintenance of signals based on memory cell groupings reduces overall power consumption compared to conventional approaches that activate all signals repeatedly.
Solution Approach 2:
The patent precharges data lines only once before a series of sensing operations rather than precharging between each sensing stage. This preliminary action reduces both the time required for multiple sensing operations and the power consumption associated with repeated precharging, while still enabling sequential sensing of different memory cell groups.
2Loss of time
If access line signals are maintained activated during sequential sensing stages, then memory operation time is reduced, but power consumption increases
Solution Approach 1:
The patent applies different signal maintenance strategies to different access line signals based on their specific usage requirements. Signals associated with currently active memory cell groups are maintained activated, while signals for inactive groups are deactivated. This localized differentiation reduces overall power consumption while maintaining fast operation for active sensing stages.
Solution Approach 2:
The patent maintains access line signals activated for a longer duration than the minimum required for a single sensing operation, keeping them active across multiple sensing stages. This excessive action in terms of signal duration eliminates the time penalty of repeated activation, and power consumption is managed through selective maintenance based on memory cell groupings rather than universal continuous activation.
3Measurement precision
If data lines are precharged between sensing stages, then sensing accuracy is maintained, but memory operation time and power consumption increase
Solution Approach 1:
The patent performs data line precharging as a preliminary action before a series of sensing operations rather than between each sensing stage. This single preliminary precharge maintains sensing accuracy for subsequent sensing stages while eliminating the time and power overhead of repeated precharging operations.
Solution Approach 2:
The patent maintains data lines in a charged state continuously across multiple sensing stages through the preliminary precharging action, enabling continuous sensing operations without interruption for re-precharging. This continuous charged state preserves sensing accuracy while reducing overall operation time and power consumption compared to intermittent precharging approaches.
Data Source
AI summary
Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.