Memory Cell Sensing Circuit Parasitic Capacitance Management
Solution Overview
Problem
Existing memory systems face inaccuracies in reading data due to parasitic capacitances among word lines, which cause fluctuations in voltage or current at other gate lines, leading to unreliable data retrieval.
Innovation Solution
A memory system that includes a memory controller with a pair of transistors to electrically couple a voltage source and a sensor to a bit line, using specific pulse patterns to manage these fluctuations by coupling the voltage source during a set time period and decoupling the sensor, allowing voltages or currents at other gate lines to settle before sensing data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sensor is continuously coupled to the bit line to sense current through the memory cell, then data reading accuracy is improved, but parasitic capacitances cause voltage fluctuations that lead to unreliable sensing
Solution Approach 1:
The patent implements periodic switching between sensing mode and bias mode using pulse patterns. The sensor is coupled to the bit line only during specific time windows when parasitic effects have settled, rather than continuously. This periodic action allows accurate sensing while avoiding the reliability issues caused by continuous coupling during voltage fluctuations.
Solution Approach 2:
The patent applies preliminary biasing pulses to the word line before the sensing operation. These preliminary pulses allow the parasitic capacitances to charge or discharge and settle before the actual sensing begins, ensuring that when the sensor couples to the bit line, the voltage fluctuations have already stabilized, thus improving both accuracy and reliability.
2Productivity
If high-speed pulse patterns are applied to the word line for fast memory operations, then productivity is improved, but parasitic capacitances among word lines cause voltage fluctuations that reduce measurement precision
Solution Approach 1:
The patent uses periodic pulse patterns with specific timing to apply high-speed signals to the word line while creating corresponding periodic windows for sensing. The sensing operation is synchronized to occur during stable periods between pulse transitions, maintaining both high speed operation and accurate measurement by rhythmically coordinating the sensing action with the pulse pattern.
Solution Approach 2:
The patent applies preliminary biasing pulses at controlled speeds before the actual high-speed operation begins. These preliminary actions prepare the parasitic capacitances to settle at known voltage levels, establishing a stable baseline that allows subsequent high-speed operations to be performed accurately without the parasitic effects degrading measurement precision.
3Reliability
If the sensor is decoupled from the bit line during voltage settling, then reliability is improved, but data reading speed is reduced due to additional settling time required
Solution Approach 1:
The patent implements a periodic switching scheme where the sensor alternates between coupled and decoupled states in synchronization with the word line pulse pattern. During decoupled periods, voltages settle reliably; during coupled periods, sensing occurs rapidly. This periodic rhythm maintains reliability through proper settling while preserving speed by minimizing the duration of the decoupled state and overlapping sensing with stable periods.
Solution Approach 2:
The patent performs preliminary decoupling and settling actions in a controlled manner before the actual sensing begins. By anticipating the need for settling and preparing the circuit state in advance with preliminary biasing pulses, the system ensures reliable voltage stabilization occurs before sensing starts, eliminating the need for extended settling time during the critical measurement phase and thus maintaining high data reading speed.
Data Source
AI summary
Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell and ii a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.