Memory Sensing Circuit Reference Bit Line
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Solution Overview
Problem
Existing SRAM bit cells, particularly dual-port 2P-8T bit cells, face limitations in read operation speed and real estate usage due to the requirement of full-voltage swing on bit lines and bit bar lines, which restricts the number of bit cells that can be accommodated per line and increases power consumption.
Innovation Solution
The introduction of a reference bit line (rBL) signal allows for the use of a differential sensing amplifier, enabling read operations with a smaller voltage drop, thereby accommodating up to 256 dual-port bit cells per line without the need for additional I/O circuits, and averaging plural rBL signals to derive a steady discharging rate for reliable read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-voltage swing is used on bit lines for read operations, then read operation reliability is improved, but read operation speed decreases and power consumption increases
Solution Approach 1:
The patent changes the voltage parameter from full-voltage swing to a smaller voltage drop by using a pre-charged reference bit line (rBL) as a comparison reference. The sensing amplifier detects the voltage difference between the actual bit line (BL) and the pre-charged reference bit line (rBL), enabling reliable read operations with reduced voltage swing requirements, thereby improving read operation speed while maintaining reliability.
2Reliability
If full-voltage swing is used on bit lines for read operations, then read operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent reduces the voltage swing parameter from full-voltage to a smaller voltage drop by comparing the actual bit line voltage against a pre-charged reference bit line. This parameter change enables the sensing amplifier to detect data with reduced power consumption while maintaining read operation reliability through differential voltage comparison.
3Measurement precision
If full-voltage swing is required on bit lines, then read operation accuracy is improved, but the number of bit cells that can be accommodated per line decreases
Solution Approach 1:
The patent changes the voltage parameter from full-voltage swing to a smaller voltage drop by using a pre-charged reference bit line (rBL) as comparison reference. This enables the sensing amplifier to maintain read operation accuracy through differential voltage detection while reducing the voltage requirements, thereby allowing more bit cells to be accommodated per line and increasing storage density.
4Quantity of substance
If additional I/O circuits are added to accommodate more bit cells, then storage density is improved, but device complexity and real estate usage increase
Solution Approach 1:
The patent uses a reference bit line (rBL) that is pre-charged to Vdd within the same memory array structure to serve as the comparison reference for the sensing amplifier. This self-service approach eliminates the need for external I/O circuits or additional reference voltage generation circuits, thereby increasing storage density without adding device complexity or real estate requirements.
5Quantity of substance
If additional I/O circuits are added to accommodate more bit cells, then storage density is improved, but real estate usage increases
Solution Approach 1:
The reference bit line (rBL) is integrated within the memory array structure and pre-charged to Vdd, serving as the comparison reference for the sensing amplifier. This eliminates the need for external I/O circuits or additional reference voltage generation hardware, thereby achieving higher storage density without increasing real estate usage.
Data Source
AI summary
A memory device includes a first memory array comprising a first bit cell configured to store a first logical state; and a reference signal provision (RSP) unit, coupled to the first memory array, and configured to provide a first reference signal that represents an average of a discharging rate and a leakage rate of a second memory array. In an embodiment, the first logical state stored by the first bit cell is read out using the first reference signal.