Memory Sensing Circuitry Parity Calculation
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Solution Overview
Problem
Existing memory systems require data transfer via input/output lines to perform parity calculations, which consumes power and resources, and lacks efficient methods for error detection and correction within the memory array.
Innovation Solution
The use of sensing circuitry within the memory array to perform parity calculations and error correction without transferring data via input/output lines, by determining parity values using XOR operations and storing them in adjacent memory cells, allowing for parallel processing and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred via input/output lines to perform parity calculations, then error detection and correction can be performed, but power consumption and system resources increase
Solution Approach 1:
The patent combines the parity calculation function with the existing sensing circuitry within the memory array. The sense amplifiers that are already present for reading data are utilized to perform XOR operations for parity determination, merging two functions into a single circuit component. This eliminates the need for separate data transfer paths and dedicated parity calculation units, thereby reducing power consumption while maintaining error detection and correction capabilities
Solution Approach 2:
The patent extracts the parity calculation operation from the external processing system and relocates it directly into the memory array's sensing circuitry. By performing parity calculations in-place within the memory device using the sensing amplifiers, the system eliminates the need to transfer data out via input/output lines for parity computation, thus reducing power consumption and resource usage while preserving the reliability function
2Reliability
If data is transferred via input/output lines to perform parity calculations, then parity determination can be performed, but system resources and processing time increase
Solution Approach 1:
The sensing circuitry is designed to perform both data sensing and parity calculation functions. The sense amplifiers read data bits from memory cells and simultaneously perform XOR operations to determine parity bits, merging multiple functions into a single integrated circuit block. This reduces device complexity by eliminating separate data transfer paths and dedicated parity calculation hardware
Solution Approach 2:
The sensing circuitry within the memory array is designed with multi-functionality, serving both as data readout amplifiers and as parity calculation units. The same sensing amplifiers that retrieve data from memory cells are also configured to perform logical XOR operations for parity determination, thereby reducing system resource requirements while maintaining data integrity through error detection and correction
3Use of energy by moving object
If parity calculations are performed using sensing circuitry within the memory array, then power consumption is reduced, but the circuitry must perform multiple logical operations
Solution Approach 1:
The patent merges the data sensing operation with the parity calculation operation into a single integrated process performed by the sensing circuitry. The sense amplifiers simultaneously perform data bit reading and XOR logical operations to determine parity bits, combining multiple functions into one unified circuit operation that reduces overall power consumption despite the increased logical complexity
Data Source
AI summary
The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.