Memory Sensing Circuitry for In-Array Logic Without Bus Transfer
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in efficiently performing logical operations while minimizing power consumption and chip size, particularly in processor-in-memory (PIM) devices where increased power usage and larger chip sizes are drawbacks.
Innovation Solution
The implementation of sensing circuitry that performs logical operations directly within the memory array, using a primary latch coupled to a sense line to sense memory cells, perform intermediate operations, and accumulate results in a secondary latch without requiring sense line address access, thus reducing power consumption and enabling parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If processing resources are implemented external to the memory array with data accessed via a bus, then chip size is reduced, but processing performance deteriorates due to time and power consumption in data transfer
Solution Approach 1:
The patent merges the processing resources (functional units) directly into the memory array structure, allowing data to be processed in-place without external bus transfers. This integration enables the memory array to perform logical operations internally, combining storage and processing functions in a single unified structure.
Solution Approach 2:
The patent introduces a new dimensional aspect by implementing processing capabilities within the memory array's internal structure rather than relying on external processing. This adds a processing dimension to the traditionally storage-only memory architecture, enabling parallel operations across multiple memory cells simultaneously.
2Productivity
If processing resources are implemented internal to the memory array (PIM device), then processing performance is improved, but chip size increases
Solution Approach 1:
The patent implements functional units that can perform multiple logical operations (AND, OR, NOT, NAND, NOR, XOR) using the same hardware structure within the memory array. This multi-functionality allows a single processing resource to handle various computational tasks, reducing the overall chip size compared to dedicated processing units for each operation type.
Solution Approach 2:
The patent divides the processing functionality into distributed functional units that are integrated throughout the memory array structure. Rather than concentrating all processing resources in a separate block, the processing capabilities are segmented and distributed across multiple memory cell locations, enabling parallel processing while maintaining compact integration.
3Productivity
If PIM devices are implemented, then processing efficiency is improved, but power consumption increases
Solution Approach 1:
The patent enables the memory array to perform processing operations on its own stored data without requiring external processing resources. The functional units within the memory array utilize the existing memory cell structures and signaling infrastructure to execute logical operations, eliminating the need for separate power-intensive data transfer and processing operations.
Solution Approach 2:
The patent maintains continuous operation by performing processing tasks directly within the memory array without interrupting the stored data state. The functional units operate continuously on the data already present in the memory cells, avoiding the stop-start nature of traditional fetch-process-store cycles that incur repeated power overhead.
4Device complexity
If data is transferred via bus between memory array and processing resources, then device complexity is reduced, but loss of time increases due to data transfer
Solution Approach 1:
The patent extracts the data transfer step entirely from the processing workflow by performing operations in-place within the memory array. Rather than extracting data to external processors and then returning results, the processing is performed directly where the data resides, eliminating the time-consuming bus transfer operations while maintaining relatively simple device architecture.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.