Memory Sensing Circuitry for In-Memory Logic Without Bus Transfers
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Solution Overview
Problem
Conventional processor-in-memory (PIM) devices face challenges in power consumption and increased chip size due to the need for external processing resources to perform logical operations, which also require significant data transfer across buses, leading to inefficiencies in compute functions and memory density.
Innovation Solution
The implementation of sensing circuitry within the memory array that performs logical operations without transferring data via a sense line address access, using a primary and secondary latch to accumulate results, allowing for parallelism and reduced power consumption by eliminating the need for external processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external processing resources are used to perform logical operations, then computational functionality is provided, but power consumption increases and chip size increases
Solution Approach 1:
The patent merges the memory array and sensing circuitry to perform logical operations directly within the memory device. The sensing circuitry is configured to sense memory cells and accumulate results using latch circuitry, eliminating the need for separate external processing resources. This integration allows logical operations to be performed using the existing memory and sensing infrastructure, thereby providing computational functionality without the additional power consumption and chip size overhead of external processors.
2Adaptability or versatility
If data is transferred across buses to external processing resources, then logical operations can be executed, but data transfer time and power consumption increase
Solution Approach 1:
The patent extracts the logical operation execution capability from external processing resources and relocates it directly into the sensing circuitry within the memory device. By configuring the sensing circuitry to perform logical operations on sensed memory cell data and accumulate results using latch circuitry, the system eliminates the need to transfer data across buses to external processors. This extraction and relocation of functionality keeps data processing local, significantly reducing data transfer time and associated power consumption.
3Use of energy by moving object
If sensing circuitry performs logical operations directly in the memory array, then power consumption is reduced and parallel processing capability increases, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality in the sensing circuitry, which is configured to perform both traditional sensing operations and logical operations. The same sensing circuitry that reads memory cell data is also configured to perform logical operations on that data and accumulate results using latch circuitry. This universal approach allows the sensing circuitry to handle multiple functions without requiring entirely separate dedicated logic units, thereby reducing the overall increase in device complexity while still enabling power-efficient logical operations and parallel processing capabilities.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.