Semiconductor Memory Page Buffer Sensing Node Capacitance
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Solution Overview
Problem
As the degree of integration of semiconductor memory devices improves, the area available for implementing page buffer circuits decreases, leading to a reduction in the size of sensing nodes and subsequently their capacitance, which is insufficient for reliable read or write operations.
Innovation Solution
The semiconductor memory device incorporates a page buffer circuit with sensing nodes designed using metal patterns. These sensing nodes consist of a lower metal pattern extending in a first horizontal direction and one or more upper metal patterns spaced vertically and extending in a second horizontal direction or perpendicular to it, thereby increasing the capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is improved to increase storage capacity, then the area available for page buffer circuits decreases, but the capacitance of sensing nodes becomes insufficient
Solution Approach 1:
The sensing node structure transitions from a planar single-layer configuration to a three-dimensional multi-layer configuration. The lower metal pattern extends in a first horizontal direction while upper metal patterns extend in a second horizontal direction perpendicular to the first, creating a multi-dimensional structure that increases capacitance without occupying additional planar area.
Solution Approach 2:
The upper metal patterns are positioned vertically above the lower metal pattern, with the upper patterns nested over the peripheral circuit region while the lower pattern extends into the memory cell region. This nested arrangement allows the sensing node to achieve increased capacitance by utilizing vertical stacking rather than horizontal expansion.
2Productivity
If the area of sensing nodes is reduced to fit more page buffer units, then the capacitance value decreases, but the reliability of read/write operations deteriorates
Solution Approach 1:
The invention resolves the contradiction by moving from a two-dimensional planar sensing node to a three-dimensional multi-layer sensing node. The lower metal pattern extends in a first horizontal direction and upper metal patterns extend in a second horizontal direction perpendicular to the first, creating a multi-dimensional structure that maintains sufficient capacitance while reducing the planar footprint to accommodate more page buffer units.
Solution Approach 2:
The sensing node is constructed as a composite structure combining lower and upper metal patterns in different metal layers, separated by an insulating layer. This composite arrangement allows the sensing node to achieve higher effective capacitance density by utilizing both horizontal extension and vertical stacking, enabling reliable operation with reduced area.
3Area of moving object
If the size of sensing nodes is decreased to increase integration density, then the capacitance value is reduced, but the ability to maintain data reliability is compromised
Solution Approach 1:
The invention addresses this contradiction by transitioning from a single-plane metal pattern to a multi-layer three-dimensional structure. The lower metal pattern extends in a first horizontal direction while upper metal patterns extend in a second horizontal direction perpendicular to the first, creating a multi-dimensional configuration that maintains sufficient capacitance despite reduced planar area.
Solution Approach 2:
The sensing node is segmented into distinct lower and upper metal patterns separated by an insulating layer, with each pattern contributing to the overall capacitance. This segmentation allows the structure to achieve higher capacitance density by utilizing both horizontal extension and vertical stacking, maintaining data retention reliability with reduced sensing node footprint.
Data Source
AI summary
A semiconductor memory device includes a memory cell array that is formed in a memory cell region, and a page buffer circuit that is formed in a peripheral circuit region and includes a plurality of page buffer units each including a sensing node for reading data stored in the memory cell array. The sensing node includes a lower metal pattern that extends in a first horizontal direction and one or more upper metal patterns that are spaced from the lower metal pattern in a vertical direction, electrically connected to the lower metal pattern and extend in a second horizontal direction being perpendicular to the first horizontal direction or in a direction facing away from the second horizontal direction.