Memory Subsystem Sensing Time Adjustment for 3D NAND Degradation

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Solution Overview

Problem

Memory devices, especially 3D NAND devices, experience increased bit error rates due to read window budget degradation as they undergo program erase cycles, leading to unreliable data storage and retrieval, particularly in partially functional blocks with degraded wordlines.

Innovation Solution

A memory sub-system that adaptively adjusts the default sensing time during the program verify phase to prevent read window budget degradation by determining the functional status of memory blocks and applying sensing time adjustments based on the number of program erase cycles, using a sensing time adjustment data structure to compensate for potential read errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory device uses a fixed default sensing time during program verify phase, then the operation is simple and fast, but read window budget degradation occurs leading to increased bit error rates in partially functional blocks

Engineering Contradiction:
Improvebit error rateVSAvoidsensing time adjustment mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sensing time is changed from a fixed default value to a dynamic parameter that is adjusted based on the number of program erase cycles. The memory controller selectively applies different sensing times (first sensing time for blocks with fewer PECs, second sensing time for blocks with more PECs) to adapt to degradation conditions, thereby maintaining read reliability without requiring complete redesign of the sensing mechanism.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the sensing time parameter based on the operational history of memory blocks. By monitoring the number of program erase cycles and using this information to select between different sensing times, the system adjusts a critical timing parameter to compensate for read window budget degradation while maintaining a relatively simple overall structure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the memory device performs read level optimization to compensate for degradation, then read accuracy improves, but the complexity of the control mechanism increases

Engineering Contradiction:
Improveread accuracyVSAvoidcontrol mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the sensing time adjustment function from the complex read level optimization process. Instead of implementing full read level optimization which involves multiple voltage levels and complex control logic, the invention isolates the critical timing parameter adjustment and implements it separately based on PEC count, thereby achieving read accuracy improvement with reduced control mechanism complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses a simple lookup table that maps PEC counts to sensing time values, replacing complex read level optimization tables. This simplified approach uses a more straightforward data structure and control logic, achieving the same reliability goal with less complexity in the control mechanism.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If the memory device applies longer sensing time to partially functional blocks, then read window budget degradation is compensated, but the overall operation speed decreases

Engineering Contradiction:
Improveread window budgetVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies different sensing times to different memory blocks based on their functional status and degradation level. Fully functional blocks use the default sensing time for fast operations, while partially functional blocks with significant degradation use extended sensing times. This localized adjustment ensures that reliability improvements are achieved only where needed, minimizing the impact on overall operation speed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240203504A1Sensing time adjustment for program operation in a memory device
Publication Date: 2024.06.20 MICRON TECHNOLOGY INC
  • US20240203504A1 patent drawing
  • US20240203504A1 patent drawing
  • US20240203504A1 patent drawing

AI summary

A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A sensing time adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default sensing time is adjusted by the sensing time adjustment value to generate an adjusted sensing time. The program operation on the set of vertically stacked memory cells is performed using the adjusted sensing time.