Semiconductor Memory Device Multi-Level Sensing Voltage Waveform
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently performing multi-level sensing operations, particularly in reducing read operation time and optimizing voltage application during read operations.
Innovation Solution
The semiconductor memory device incorporates a voltage generation circuit that applies a read voltage that gradually increases over time to word lines, allowing the read and write circuit to sense cell currents and determine data states by detecting changes in a sensing node's potential level, thereby reducing read operation time and improving sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single read voltage is applied to word lines during read operation, then the circuit complexity is reduced, but the sensing accuracy for multi-level data may deteriorate
Solution Approach 1:
The patent applies a read voltage that dynamically increases over time during the read operation rather than using a static voltage. This dynamic voltage approach allows a single voltage generation circuit to achieve multi-level sensing by adapting the voltage level according to the sensing progress, thereby reducing circuit complexity while maintaining sensing accuracy.
Solution Approach 2:
The patent changes the parameter of read voltage over time, starting from an initial level and gradually increasing to a final level. This parameter change enables the system to distinguish between multiple program states (erase state and multiple program states) using a single voltage waveform, avoiding the need for multiple fixed voltage levels and reducing circuit complexity.
2Measurement precision
If multiple read voltages are applied to distinguish different program states, then the sensing accuracy is improved, but the read operation time increases
Solution Approach 1:
The patent employs a continuous read voltage that gradually increases over time rather than applying multiple discrete voltage levels sequentially. This continuous action allows the sensing operation to proceed without interruption, maintaining high sensing accuracy while reducing the total read operation time compared to multi-step voltage application methods.
Solution Approach 2:
The read voltage is pre-configured to follow a specific increasing waveform that is optimized in advance to distinguish between all program states within a single read operation. This preliminary design of the voltage waveform ensures that all necessary sensing information is obtained continuously without requiring multiple separate voltage application steps.
3Productivity
If a read voltage that gradually increases is applied to word lines, then the read operation speed is improved, but the control complexity of voltage generation increases
Solution Approach 1:
The read voltage generation follows a predetermined periodic waveform that increases over time in a controlled manner. This periodic action pattern simplifies the control logic by using a repeating voltage profile, making it easier to generate the increasing voltage sequence without requiring complex real-time control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster read operations and reduces the complexity of the circuit by using a single read voltage, enhancing the memory device's ability to distinguish between different program states and improving overall performance.
Implementation Method 1
the read voltage increases as time elapses
Implementation Method 2
sensing a cell current of bit lines respectively connected to the at least one or more memory cells
Data Source
AI summary
The present technology relates to a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block including a plurality of memory cells programmed to an erase state and a plurality of program states, a voltage generation circuit configured to generate a read voltage to be applied to word lines of the memory block during a read operation, and a read and write circuit connected to bit lines of the memory block and configured to latch data by sensing a potential level of a sensing node based on a cell current of the memory cells in a predetermined time unit during the read operation, wherein the read voltage is applied to the word lines consecutively in a predetermined period and gradually increases according to a time in the predetermined period.