3D Semiconductor Memory Separation Structure for Dense Stacked Arrays
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Solution Overview
Problem
Existing two-dimensional or planar semiconductor devices face limitations in integration due to the expensive equipment required for fine pattern formation, which restricts the increase in density and productivity.
Innovation Solution
A three-dimensional semiconductor memory device is designed with peripheral circuit structures on a substrate, stacked structures with gate electrodes, a separation structure including support patterns spaced apart in the third direction, and an internal insulating layer surrounding the side surfaces of the support patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar device layout to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher integration density by utilizing the third dimension (vertical stacking) while maintaining compatibility with existing manufacturing processes through sequential layer formation.
2Quantity of substance
If fine pattern formation is used to increase integration, then device density improves, but equipment cost increases
Solution Approach 1:
Instead of increasing pattern fineness in the planar direction which requires expensive equipment, the patent achieves higher device density by stacking multiple layers vertically. This approach increases integration density through the third dimension while avoiding the need for advanced lithography equipment.
Solution Approach 2:
The three-dimensional memory structure is divided into multiple stacked layers, each containing memory cells, word lines, and bit lines. This segmentation allows independent formation of each layer using standard manufacturing processes, avoiding the need for single complex high-precision processes.
3Quantity of substance
If three-dimensional stacked structures are used, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The three-dimensional structure is segmented into repeating modular units (stacked layers) that can be formed through sequential application of similar manufacturing processes. Each layer contains segmented functional elements (memory cells, word lines, bit lines) that simplify the overall manufacturing complexity despite the increased vertical integration.
Data Source
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AI summary
A three-dimensional semiconductor memory device includes peripheral circuit structures (PS) on a substrate (10), stacked structures (ST) configured to each include gate electrodes (GE1, GE2) stacked on the peripheral circuit structures in a first direction (D1) perpendicular to a lower surface of the substrate, and to be spaced apart from each other in a second direction (D2) parallel to the lower surface of the substrate, a separation structure (SS) configured to extend between the stacked structures in a third direction (D3) intersecting the first direction and the second direction, and to include support patterns (SU) arranged to be spaced apart from each other in the third direction in the separation structure, and an internal insulating layer (ID) surrounding a side surface of each of the support patterns.