Semiconductor Memory Sequencer Parallel Erase Read Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing operations during erase processes, leading to increased latency and potential delays in data retrieval.
Innovation Solution
The semiconductor memory device incorporates a sequencer that executes operations based on command sets, allowing for the suspension or parallel execution of operations during erase processes. This is achieved by determining the relationship between target blocks for different operations, enabling efficient interrupt processes without suspending the erase operation wherever possible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sequencer executes operations sequentially during erase processes, then operation reliability is improved, but latency increases and productivity decreases
Solution Approach 1:
The sequencer dynamically adjusts its operation mode based on real-time conditions. It can switch between sequential execution (for reliability-critical operations) and parallel/suspended execution (for time-critical operations), making the system flexible and adaptive to different operational requirements
Solution Approach 2:
The system changes the execution parameter of operations by determining relationships between target blocks. Based on whether blocks are the same or different, the sequencer changes the execution mode (suspension or parallel execution), thereby optimizing both latency and reliability for different scenarios
2Speed
If the sequencer suspends erase operations for interrupt processes, then read operations can be executed timely, but productivity decreases due to operation interruptions
Solution Approach 1:
Instead of completely suspending the erase operation, the system performs partial suspension only when necessary (same target block). When target blocks differ, the erase operation continues partially or fully in parallel, maintaining productivity while still enabling timely read operations
Solution Approach 2:
The system segments the erase operation based on target block relationships. By dividing operations into those that can be parallelized (different blocks) and those requiring suspension (same block), the system optimizes both read speed and erase throughput simultaneously
3Productivity
If the sequencer executes operations in parallel, then productivity is improved, but operation complexity increases
Solution Approach 1:
The sequencer performs preliminary determination of the relationship between target blocks before executing operations. By pre-assessing whether blocks are the same or different, the system prepares the appropriate execution mode in advance, simplifying the control logic for parallel execution
Solution Approach 2:
The relationship determination mechanism acts as an intermediary between the operation request and the sequencer execution. It mediates by selecting the appropriate execution mode based on target block relationships, thereby managing complexity while enabling parallel productivity
Data Source
AI summary
A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.