Memory Operation Sequence Verification by Control Signal Counting
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Solution Overview
Problem
Memory devices may malfunction due to defects in control signals or circuit operations, which are not easily detected, leading to improper functioning.
Innovation Solution
A memory device is equipped with an operation sequence count value system that verifies the sequence of operations by counting the number of times operation control signals are toggled, using a scheduler and an operation sequence verification circuit to compare this count with expected values to detect defects and stop operations if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an operation sequence verification circuit is added to count and verify operation control signals, then the reliability of operation verification is improved, but the device complexity increases
Solution Approach 1:
An operation sequence verification circuit is introduced as an intermediary component between the scheduler and the operation execution units. This circuit counts the number of toggles of operation control signals and compares the count against expected values, thereby verifying operational correctness without requiring fundamental changes to the existing memory device architecture.
2Measurement precision
If the operation sequence verification circuit continuously monitors and counts all operation control signals, then the defect detection capability is improved, but the loss of time for operation verification increases
Solution Approach 1:
The verification circuit performs counting and comparison operations in parallel with the normal operation execution. By preliminarily establishing the expected toggle counts for different operation sequences and continuously monitoring in real-time, the system can immediately detect deviations without pausing or slowing down the memory device operations.
3Measurement precision
If the verification circuit compares operation sequence count values with expected count values, then the accuracy of defect identification is improved, but the device complexity increases
Solution Approach 1:
The operation sequence verification circuit autonomously performs the complete verification process including counting operation control signal toggles, comparing counts against pre-stored expected values, and generating defect identification results. The circuit serves itself by maintaining internal state information and making independent verification decisions without requiring external control or intervention.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of planes, a peripheral circuit configured to perform an operation with respect to the plurality of planes, and a scheduler configured to control the peripheral circuit, The scheduler also is configured to generate a plurality of operation control signals toggling according to a sequence of sub-operations included in the operation and to perform the operation according to the plurality of operation control signals The memory device also includes an operation sequence verification circuit configured to verify a defect of the operation based on the result of comparing an operation sequence count value obtained by counting the number of times by which a selected operation control signal among the plurality of operation control signals is toggled with an expected count value.