Multi-site Memory Testing via SERDES Interconnection
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Solution Overview
Problem
The increasing complexity of computer memory devices with dense architectures poses a challenge for efficient testing, particularly in serial IO ports, where manufacturers face difficulties in identifying defective units and determining the nature of flaws within multiple interconnected devices, leading to high testing costs and complexity.
Innovation Solution
A method and apparatus for multi-site testing of computer memory devices and serial IO ports, utilizing serializer-deserializer (SERDES) circuit innovation, which allows for simultaneous testing of multiple devices through interconnection, error detection, and error localization, incorporating test generators, error checkers, and switching elements to establish test paths and communicate error information among devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory devices are interconnected for simultaneous testing, then testing efficiency and productivity improve, but device complexity and difficulty of detecting flaws increase
Solution Approach 1:
The testing system is segmented into multiple independent test channels, each capable of independently testing a memory device. Each channel includes its own test pattern generator, serializer, and error checker, allowing parallel testing while maintaining independent control and simplified diagnostics for each channel.
Solution Approach 2:
A central controller acts as an intermediary that coordinates the multiple test channels, manages test pattern distribution, and aggregates test results. This intermediary component simplifies the overall system control by centralizing the coordination logic while allowing individual channels to operate independently.
2Reliability
If more test circuitry is added to memory devices, then testing capability improves, but silicon area available for memory cells decreases
Solution Approach 1:
The memory device's existing serial interface circuits (serializer and deserializer) are made multi-functional by enabling them to operate in both normal data transmission mode and test mode. The same physical circuits perform dual purposes: regular memory operations during normal use and test pattern transmission during testing, eliminating the need for dedicated test circuitry.
Solution Approach 2:
The memory device performs self-testing by using its own internal test pattern generator and error checking circuits. The device tests itself without requiring external test equipment connected to each device, reducing the need for additional test circuitry while maintaining comprehensive testing capability.
3Ease of manufacture
If traditional board testing methods are used, then manufacturing process is simple, but testing cost and time increase
Solution Approach 1:
Testing is performed at the board level before final assembly and shipping, allowing defective boards to be identified and removed early in the manufacturing process. This preliminary testing prevents defective products from reaching customers and allows for efficient batch processing of multiple boards simultaneously.
Solution Approach 2:
Multiple memory boards are connected together to form a test network where boards serve both as devices under test and as test equipment for other boards. This merging of test and device functions allows parallel testing of multiple boards using a single test system, significantly reducing total testing time and cost.
Data Source
AI summary
A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.