Memory Serializer Architecture for Parallel-to-Serial NAND Output
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Solution Overview
Problem
Current memory devices face inefficiencies in converting parallel data from memory cell arrays into serial data for effective output, particularly in NAND-type flash memory systems, where data serialization and deserialization processes are not optimized for seamless data transfer.
Innovation Solution
The implementation of a serializer architecture that includes multiple FIFO circuits and latch circuits to selectively convert and output serial data from parallel data lines, enhancing data processing efficiency by utilizing parallel storage devices and selectors to manage data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a serializer converts parallel data from memory cell arrays into serial data, then data transfer efficiency is improved, but device complexity increases due to the need for multiple FIFO circuits and latch circuits
Solution Approach 1:
The serializer is divided into multiple independent FIFO circuits (first FIFO circuit, second FIFO circuit) that can operate in parallel. Each FIFO circuit handles a portion of the parallel data, converting it to serial data independently. This segmentation allows the system to maintain high data transfer efficiency while managing complexity through modular design, as each FIFO circuit is a standardized building block.
Solution Approach 2:
The latch circuit is integrated within the serializer architecture, nesting the latching function inside the existing FIFO circuit structure. The latch circuit receives serial data from the FIFO circuits and performs latching operations without requiring a completely separate external circuit block. This nesting reduces overall device complexity by consolidating functions within the serializer boundary.
2Productivity
If multiple FIFO circuits are used to selectively output serial data, then data processing efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The use of multiple FIFO circuits segmented into first and second FIFO circuits allows each circuit to be manufactured as a standardized module. This segmentation enables modular manufacturing processes where identical or similar FIFO circuit blocks can be replicated and integrated, reducing overall manufacturing complexity despite the increased number of components.
Solution Approach 2:
The FIFO circuits are designed with universal functionality to handle different data sources (first data line, second data line) and produce standardized serial output. This multi-functionality allows the same FIFO circuit design to be reused multiple times in the serializer, simplifying the manufacturing process by reducing the need for custom-designed circuits for each function.
3Productivity
If parallel data is converted into serial data with selective output, then data output optimization is improved, but processing latency increases
Solution Approach 1:
The FIFO circuits perform preliminary serialization of parallel data before the final selection and output stage. By converting parallel data to serial data in advance within each FIFO circuit, the system prepares data for efficient transmission without requiring complex real-time conversion during the selection process, thereby reducing overall processing latency.
Solution Approach 2:
The latch circuit maintains continuous operation by latching serial data from the FIFO circuits without interrupting the data flow. This continuous latching action ensures that data processing remains uninterrupted, minimizing idle time and reducing processing latency while maintaining optimized data output.
Data Source
AI summary
A data output device includes: a plurality of storage devices coupled in parallel to store input data, and having a storage region with a predetermined depth; and a selector suitable for selecting an output of any one storage device among the plurality of storage devices.