Memory Serializer Circuit for High-Rate Single-Line Data Transfer
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently converting parallel data to serial data for transmission, particularly in maintaining high data rates while minimizing power consumption and reducing the number of transmission lines.
Innovation Solution
A serializer is introduced that combines multiple clocks with specific phase differences and parallel data using Boolean logic circuits and multiplexers to convert parallel data into serial data, reducing unnecessary power consumption and maintaining uniform performance regardless of clock duty ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel transmission scheme is used to transmit multiple data simultaneously through multiple transmission lines, then data rate is improved, but device complexity and cost increase due to increased number of transmission lines
Solution Approach 1:
The patent merges multiple parallel data streams into a single serial data stream using a serializer. The serializer combines data from multiple transmission lines into one line, reducing the number of transmission lines required while maintaining high data transfer capability through time-division multiplexing.
Solution Approach 2:
The patent transitions from spatial parallelism (multiple transmission lines transmitting simultaneously) to temporal parallelism (single transmission line transmitting sequentially at different time slots). This dimensional change allows high data rates to be achieved through increased clock frequency and time-division multiplexing rather than through multiple physical lines.
2Device complexity
If serial transmission scheme is used to transmit data sequentially through one transmission line, then device complexity and cost are reduced, but data rate deteriorates
Solution Approach 1:
The patent employs periodic clock signals with specific phase relationships to control the serialization process. Multiple clocks with defined phase differences are used to systematically alternate between different data sources, creating a periodic pattern of data transmission that maximizes the utilization of the single transmission line.
Solution Approach 2:
The patent uses dynamic clock phase adjustment and multiplexer switching to adaptively manage data flow. The system dynamically selects which data source to transmit based on clock phase and control signals, enabling flexible and efficient serialization that maintains high data rates despite using a single transmission line.
3Adaptability or versatility
If multiple clocks with different duty ratios are used in serialization, then flexibility in clock generation is improved, but performance uniformity deteriorates due to varying data acquisition timing
Solution Approach 1:
The patent intentionally uses asymmetric clock signals with different duty ratios (e.g., 60/40, 70/30, or other non-50/50 splits) while maintaining uniform performance. The serialization logic is designed to correctly interpret and process data regardless of the specific duty ratio, allowing flexible clock generation while preserving reliable and uniform data acquisition across all clock configurations.
Data Source
AI summary
An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.