Memory Set Circuit for Duty-Cycle Training Data Gating
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Solution Overview
Problem
The duty cycle deviation of clock signals in Dynamic Random Access Memory (DRAM) chips, caused by generation, transmission, and internal processing, leads to inefficiencies and power consumption issues.
Innovation Solution
A memory device with a set circuit that enables or disables a first data bus based on a set signal, allowing for different operation modes to output corresponding data, and includes a parallel-to-serial conversion circuit to generate serial data bits, with clock cycles adjusted to prevent overlap and ensure accurate sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the data bus is enabled in both normal read mode and duty cycle training assist mode, then data can be read in normal mode, but power consumption increases and memory area is wasted
Solution Approach 1:
The data bus is dynamically enabled or disabled based on the current operation mode. In normal read mode, the data bus is enabled to allow data reading. In duty cycle training assist mode, the data bus is disabled to save power, as the memory outputs preset data bits without requiring data bus access. This dynamic control resolves the contradiction by adapting the data bus state to operational needs.
Solution Approach 2:
Different operation modes are provided with different data bus states. The set circuit selectively enables or disables the data bus based on the mode register, creating mode-specific behavior. This allows the memory to optimize power consumption in training mode while maintaining full functionality in normal mode.
2Use of energy by stationary object
If the data bus is disabled in duty cycle training assist mode, then power consumption is reduced and memory area is saved, but data reading capability is lost
Solution Approach 1:
The data bus state is dynamically adjusted based on operation mode. The set circuit, controlled by the mode register, enables the data bus in normal read mode for data reading capability and disables it in duty cycle training assist mode for power saving. This dynamic switching resolves the contradiction by providing the appropriate data bus state for each operational context.
3Adaptability or versatility
If a separate circuit is added for duty cycle training assist mode, then mode functionality is improved, but device complexity increases
Solution Approach 1:
The set circuit serves multiple functions: it controls data bus enable/disable in normal read mode, generates preset data bits in duty cycle training assist mode, and is controlled by the mode register. This multi-functional design resolves the contradiction by achieving mode-specific functionality through a single integrated circuit rather than separate dedicated circuits for each mode.
Solution Approach 2:
The set circuit merges the data bus control function and preset data bit generation function into a single circuit component. This consolidation reduces device complexity by eliminating the need for separate circuits for each function, while still providing complete mode functionality through the integrated design.
4Area of stationary object
If the first data bus is shared between modes, then memory area is saved, but signal integrity may be affected
Solution Approach 1:
The data bus is dynamically enabled or disabled based on operation mode. In normal read mode, the data bus is enabled for data reading with full signal integrity requirements. In duty cycle training assist mode, the data bus is disabled, preventing signal interference. This dynamic control maintains signal integrity by ensuring the data bus is only active when needed for its intended purpose.
Data Source
AI summary
A memory includes: a plurality of storage cells arranged in an array, configured such that when a storage cell is selected, data stored in the storage cell is read out from a bit line to a first data bus; and a set circuit, connected to the first data bus to receive a set signal, and configured to enable the first data bus based on the set signal and output a first data bit when the memory is in a first mode, or disable the first data bus based on the set signal and output a preset data bit when the memory is in a second mode, where the first mode is a normal read mode, and the second mode is a duty cycle training assist mode. In this way, the first data bus can be selectively enabled or disabled in different operation modes of the memory to output corresponding data.