Memory Shadow Logic ATPG Using Multiplexer Delay Alignment
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Solution Overview
Problem
Existing methods for testing memory shadow logic face challenges in accurately detecting faults due to mismatched propagation delays and voltage differentials between test and functional modes, leading to potential under/over-testing and performance penalties.
Innovation Solution
The proposed solution involves a system and method for automated test pattern generation that includes a test memory cell and a test circuit to enable and disable data-storage cells during test mode, ensuring matching memory access times and voltage differentials, using additional rows and control mechanisms to select voltage differentials and block word lines, thereby aligning test and functional modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external memory bypass implementation is used to test shadow logic without accessing memory, then stuck-at faults in shadow logic can be detected, but propagation delay mismatch between test pattern generator and actual functional path leads to under/over-testing and performance penalty
Solution Approach 1:
The patent introduces a multiplexer as an intermediary component between the memory output and the test pattern generator. This multiplexer allows selective switching between memory output data and test pattern generator data, enabling the test system to compensate for propagation delay mismatches while maintaining accurate fault detection in shadow logic circuits.
2Reliability
If internal asynchronous bypass implementation is used with multiplexer inserted into memory, then stuck-at faults in shadow logic can be detected with lower timing penalty, but propagation delay between ATPG test path and actual functional path still does not match
Solution Approach 1:
The patent implements dynamic control of the multiplexer selection based on test mode requirements. The multiplexer is controlled by a test mode signal that dynamically switches between memory output and test pattern generator output, allowing the system to adapt propagation delays in real-time during different testing phases while maintaining precise timing alignment.
3Loss of time
If internal synchronous bypass approach with sequential logic delay circuit is used, then access time in ATPG test mode matches functional mode, but sense amplifier reaction time cannot be matched under all process conditions
Solution Approach 1:
The patent changes the operational parameters of the memory system during testing by enabling special test modes that modify access timing and voltage differential characteristics. The multiplexer control mechanism adjusts data selection based on these parameter changes, allowing the system to maintain both access time matching and voltage differential matching under various process conditions.
Data Source
AI summary
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.