Memory Shadow Logic Bypass Testing for At-Speed Fault Coverage
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Solution Overview
Problem
Existing testing methods for shadow logic in memory circuits, such as ROM, TCAM, and HistoRAM, are insufficient as they fail to detect certain types of errors due to varying delays caused by process, voltage, and temperature variations, and are not applicable to memory types lacking data inputs.
Innovation Solution
A memory circuit design with a bypass mode that allows direct input of test patterns to shadow logic, utilizing self-timing mechanisms to emulate worst-case delays, enabling isolated testing of shadow logic independent of the memory array operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow logic is tested through normal memory access operations, then the testing process is simple, but transient faults and at-speed errors cannot be detected due to varying delays from process, voltage, and temperature variations
Solution Approach 1:
The testing architecture is segmented into two independent modes: normal memory access mode for regular operations and shadow logic test mode for dedicated testing. The test mode separates the shadow logic testing path from the memory array, allowing independent control and observation of shadow logic behavior without interference from memory operations.
Solution Approach 2:
A test controller acts as an intermediary between the test pattern generator and the shadow logic. The test controller manages the bypass mode activation, coordinates the test patterns, and controls the timing signals to ensure accurate shadow logic testing while isolating it from normal memory operations.
2Adaptability or versatility
If existing testing methods are used for memory types without data inputs (ROM, TCAM, HistoRAM), then the testing process is straightforward, but shadow logic cannot be properly tested due to lack of data input capability
Solution Approach 1:
The testing architecture is designed to be universal across different memory types (SRAM, ROM, TCAM, HistoRAM) by implementing a mode-dependent testing approach. The same test controller and bypass mechanism work for all memory types, with the key difference being whether the memory array is bypassed or accessed normally during testing.
Solution Approach 2:
The testing system dynamically adapts its behavior based on the memory type and test requirements. The bypass mode can be activated or deactivated depending on whether the memory array should be accessed during testing, allowing the same hardware to accommodate different memory architectures with different data input characteristics.
3Productivity
If shadow logic is tested in isolation without emulating memory access delays, then the testing is fast and simple, but the testing does not reflect real-world performance conditions
Solution Approach 1:
The self-timing circuit performs preliminary actions by pre-calculating and generating the necessary timing signals before the actual shadow logic testing begins. The dummy decoder and dummy memory elements are activated in advance to establish the correct timing relationships, ensuring that the shadow logic is tested under conditions that accurately reflect real-world memory access delays.
Solution Approach 2:
The self-timing circuit creates a copy of the memory access timing behavior using dummy memory elements and decoders. This copy replicates the timing characteristics of actual memory operations without requiring the real memory array to be accessed, allowing fast testing while maintaining measurement precision through accurate delay emulation.
Data Source
AI summary
Disclosed herein is a self-timed memory circuit with a bypass mode for testing output shadow logic. The circuit is applicable to various memory types, including ROM, HistoRAM, and TCAM. In normal operation, the memory array outputs data through sense amplifiers and latches, controlled by self-timing circuitry. The output then passes through shadow logic for additional processing. The bypass mode allows direct testing of the shadow logic by inputting test patterns (address bits or search keys) that bypass the memory array. These test signals use the same self-timing mechanisms as normal operations, providing for accurate timing representation. This approach enhances fault coverage for shadow logic, enabling detection of transient faults and at-speed errors that might be missed by conventional static testing.