High Density Memory Structure with Shared Global Bit Lines
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Solution Overview
Problem
Current memory structures face challenges in achieving high memory cell density and efficient access while minimizing chip area and cost, particularly in volatile and non-volatile memory devices like SRAM and flash memory.
Innovation Solution
The proposed memory structure connects local bit lines to global bit lines through switch elements, allowing direct read and write signals to pass between local and global bit lines in a single I/O phase, and shares peripheral circuits among multiple banks to reduce current load and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage capacity is improved, but access efficiency and speed may deteriorate due to longer signal paths and increased complexity
Solution Approach 1:
The memory structure is divided into multiple banks, each with its own local bit lines connected to shared global bit lines through switch elements. This segmentation allows parallel access to different banks, maintaining high access efficiency while increasing overall memory density through the use of multiple independent memory arrays.
Solution Approach 2:
The patent introduces a hierarchical bit line structure with local and global levels, adding a dimensional layer to the traditional single-level bit line architecture. This multi-level approach allows memory cells to be organized in three-dimensional space, increasing density without proportionally increasing access time, as local bit lines provide short-distance access while global bit lines handle long-distance signal transmission.
2Quantity of substance
If more peripheral circuits are added to support higher density, then memory functionality is improved, but chip area and cost increase
Solution Approach 1:
Multiple banks share common global bit lines and peripheral circuits, merging resources that would otherwise be duplicated in each bank. This sharing approach reduces the total chip area required for peripheral components while supporting higher memory density through the use of multiple banks with shared infrastructure.
Solution Approach 2:
The global bit lines and peripheral circuits are designed to serve multiple banks simultaneously, giving these components universal functionality. This multi-functionality allows the same physical circuits to support a larger memory capacity without proportionally increasing chip area, as the peripheral infrastructure is reused across multiple memory banks.
3Quantity of substance
If current load is increased to drive more memory cells, then memory capacity is improved, but power consumption and heat generation worsen
Solution Approach 1:
The memory is divided into multiple banks that can be accessed independently, allowing current load to be distributed across different banks rather than concentrating all current demands on a single set of bit lines. This segmentation reduces peak current requirements and power consumption while maintaining high memory capacity through the aggregate storage of multiple banks.
Solution Approach 2:
Not all banks need to be accessed simultaneously; the system can activate only the necessary subset of banks for each operation. This partial action approach reduces actual power consumption below the maximum possible load, as current is drawn only from the banks that are currently being accessed, while the overall memory capacity remains high due to the presence of multiple banks.
Data Source
AI summary
A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.