Multi-Channel Semiconductor Memory Shared Bus Architecture
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Solution Overview
Problem
Conventional multi-channel semiconductor memory devices require a large number of through-silicon vias for dedicated command and address signal transfer, leading to increased chip die size, reduced yield, and higher costs.
Innovation Solution
Implementing a shared bus system for row command and address signal transfer between stacked channel memories, reducing the need for dedicated through-silicon vias and minimizing the number of signal bus lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated command and address transfer lines are used for each channel memory, then signal transfer reliability is improved, but the number of through-silicon vias increases
Solution Approach 1:
The patent merges the command and address transfer lines of multiple channel memories into shared buses. Specifically, multiple channel memories share common command buses and address buses, eliminating the need for dedicated transfer lines for each channel. This reduces the total number of through-silicon vias required while maintaining signal transfer reliability through proper bus arbitration and timing control.
Solution Approach 2:
The patent implements universal buses that serve multiple channel memories simultaneously. A single command bus or address bus can transfer signals to any of the connected channel memories, making the transfer lines multi-functional. This universality reduces the overall quantity of transfer lines and through-silicon vias needed in the multi-channel memory system.
2Adaptability or versatility
If the number of through-silicon vias is increased, then signal transfer capability is improved, but chip die size increases
Solution Approach 1:
By merging multiple dedicated transfer lines into shared command buses and address buses, the patent reduces the total number of through-silicon vias required. This merging approach maintains adequate signal transfer capability for all channel memories while significantly reducing the chip die area occupied by via structures and associated routing.
3Productivity
If dedicated transfer lines are used for each channel, then signal transfer efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple dedicated transfer lines into shared buses, reducing the number of through-silicon vias that need to be manufactured. This merging reduces manufacturing complexity and cost, as fewer vias require fewer fabrication steps, less material, and simpler alignment processes while still maintaining efficient signal transfer through proper bus management.
Data Source
AI summary
Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.